Re: [PATCH v2 05/10] mmc: sunxi: Support MMC DDR52 transfer mode with new timing mode

From	Maxime Ripard <maxime.ripard@free-electrons.com>
Newsgroups	linux.kernel
Subject	Re: [PATCH v2 05/10] mmc: sunxi: Support MMC DDR52 transfer mode with new timing mode
Date	2017-07-21 09:30 +0200
Message-ID	<u5AxQ-1LL-7@gated-at.bofh.it> (permalink)
References	<u5aDn-1w5-3@gated-at.bofh.it> <u5aDo-1w5-7@gated-at.bofh.it>
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On Thu, Jul 20, 2017 at 11:44:47AM +0800, Chen-Yu Tsai wrote:
> The MMC controller can support DDR52 transfers under the new timing
> mode. According to the BSP kernel, the module clock has to be double
> the card clock, regardless of the bus width. The default timings in
> the hardware can be used.
> 
> This also reworks the code setting the internal divider, getting rid
> of a extra conditional.
> 
> Signed-off-by: Chen-Yu Tsai <wens@csie.org>

Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>

Thanks!
Maxime

-- 
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com

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[PATCH v2 05/10] mmc: sunxi: Support MMC DDR52 transfer mode with new timing mode Chen-Yu Tsai <wens@csie.org> - 2017-07-20 05:50 +0200
  Re: [PATCH v2 05/10] mmc: sunxi: Support MMC DDR52 transfer mode  with new timing mode Maxime Ripard <maxime.ripard@free-electrons.com> - 2017-07-21 09:30 +0200

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