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Re: [PATCH 10/17] RISC-V: Atomic and Locking Code

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On Wed, Jul 12, 2017 at 08:40:49PM +0800, Boqun Feng wrote:
[...]
> > +/**
> > + * set_bit - Atomically set a bit in memory
> > + * @nr: the bit to set
> > + * @addr: the address to start counting from
> > + *
> > + * This function is atomic and may not be reordered.  See __set_bit()
> 
> This is incorrect, {set,change,clear}_bit() can be reordered, see
> Documentation/memory-barriers.txt, they are just relaxed atomics. But I
> think you just copy this from x86 code, so maybe x86 code needs help
> too, at least claim that's only x86-specific guarantee.
> 
> > + * if you do not require the atomic guarantees.
> > + *
> > + * Note: there are no guarantees that this function will not be reordered
> > + * on non x86 architectures, so if you are writing portable code,
> > + * make sure not to rely on its reordering guarantees.
> > + *

Hmmm.. the claim is right here ;-/

As your implementation is relax semantics, you'd better rewrite the
comment ;-)

Regards,
Boqun

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RISC-V Linux Port v6 Palmer Dabbelt <palmer@dabbelt.com> - 2017-07-12 03:40 +0200
  [PATCH 17/17] RISC-V: Build Infastructure Palmer Dabbelt <palmer@dabbelt.com> - 2017-07-12 03:40 +0200
  [PATCH 07/17] irqchip: New RISC-V PLIC Driver Palmer Dabbelt <palmer@dabbelt.com> - 2017-07-12 03:40 +0200
  [PATCH 08/17] tty: New RISC-V SBI console driver Palmer Dabbelt <palmer@dabbelt.com> - 2017-07-12 03:40 +0200
  [PATCH 15/17] RISC-V: Paging and MMU Palmer Dabbelt <palmer@dabbelt.com> - 2017-07-12 03:40 +0200
  Re: RISC-V Linux Port v6 Arnd Bergmann <arnd@arndb.de> - 2017-07-12 10:00 +0200
    Re: RISC-V Linux Port v6 "Luis R. Rodriguez" <mcgrof@kernel.org> - 2017-07-12 16:00 +0200
    Re: RISC-V Linux Port v6 Will Deacon <will.deacon@arm.com> - 2017-07-12 20:00 +0200
      Re: RISC-V Linux Port v6 Arnd Bergmann <arnd@arndb.de> - 2017-07-12 21:40 +0200
  Re: [PATCH 16/17] RISC-V: User-facing API James Hogan <james.hogan@imgtec.com> - 2017-07-12 13:10 +0200
    Re: [PATCH 16/17] RISC-V: User-facing API Palmer Dabbelt <palmer@dabbelt.com> - 2017-07-12 18:30 +0200
      Re: [PATCH 16/17] RISC-V: User-facing API James Hogan <james.hogan@imgtec.com> - 2017-07-12 19:20 +0200
        Re: [PATCH 16/17] RISC-V: User-facing API Palmer Dabbelt <palmer@dabbelt.com> - 2017-07-14 00:00 +0200
  Re: [PATCH 10/17] RISC-V: Atomic and Locking Code Boqun Feng <boqun.feng@gmail.com> - 2017-07-12 14:50 +0200
  Re: [PATCH 10/17] RISC-V: Atomic and Locking Code Boqun Feng <boqun.feng@gmail.com> - 2017-07-12 14:50 +0200
    Re: [PATCH 10/17] RISC-V: Atomic and Locking Code Peter Zijlstra <peterz@infradead.org> - 2017-07-12 15:00 +0200
    Re: [PATCH 10/17] RISC-V: Atomic and Locking Code Palmer Dabbelt <palmer@dabbelt.com> - 2017-07-12 19:20 +0200
  Re: [PATCH 10/17] RISC-V: Atomic and Locking Code Arnd Bergmann <arnd@arndb.de> - 2017-07-12 15:20 +0200

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