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Groups > linux.kernel > #1619929
| From | Kishon Vijay Abraham I <kishon@ti.com> |
|---|---|
| Newsgroups | linux.kernel |
| Subject | [PATCH 07/32] phy: sun4i-usb: support automatically switch PHY0 route to MUSB/HCI |
| Date | 2017-04-10 15:30 +0200 |
| Message-ID | <tuHyj-1bY-37@gated-at.bofh.it> (permalink) |
| References | <tuHoB-18n-5@gated-at.bofh.it> |
| Organization | linux.* mail to news gateway |
From: Icenowy Zheng <icenowy@aosc.xyz>
On newer Allwinner SoCs (H3 and after), the PHY0 node is routed to both
MUSB controller for peripheral and host support (the host support is
slightly broken), and a pair of EHCI/OHCI controllers, which provide a
better support for host mode.
Add support for automatically switch the route of PHY0 according to the
status of dr_mode and id det pin.
Only H3 have this function enabled in this patch, as further SoCs will
be tested later and then have it enabled.
As H5 is reusing the PHY driver of H3, this function is also enabled.
Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz>
Acked-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
---
drivers/phy/phy-sun4i-usb.c | 50 ++++++++++++++++++++++++++++++---------------
1 file changed, 33 insertions(+), 17 deletions(-)
diff --git a/drivers/phy/phy-sun4i-usb.c b/drivers/phy/phy-sun4i-usb.c
index a650f283f6ff..f86a2574b953 100644
--- a/drivers/phy/phy-sun4i-usb.c
+++ b/drivers/phy/phy-sun4i-usb.c
@@ -49,12 +49,14 @@
#define REG_PHYBIST 0x08
#define REG_PHYTUNE 0x0c
#define REG_PHYCTL_A33 0x10
-#define REG_PHY_UNK_H3 0x20
+#define REG_PHY_OTGCTL 0x20
#define REG_PMU_UNK1 0x10
#define PHYCTL_DATA BIT(7)
+#define OTGCTL_ROUTE_MUSB BIT(0)
+
#define SUNXI_AHB_ICHR8_EN BIT(10)
#define SUNXI_AHB_INCR4_BURST_EN BIT(9)
#define SUNXI_AHB_INCRX_ALIGN_EN BIT(8)
@@ -110,6 +112,7 @@ struct sun4i_usb_phy_cfg {
u8 phyctl_offset;
bool dedicated_clocks;
bool enable_pmu_unk1;
+ bool phy0_dual_route;
};
struct sun4i_usb_phy_data {
@@ -269,23 +272,16 @@ static int sun4i_usb_phy_init(struct phy *_phy)
writel(val & ~2, phy->pmu + REG_PMU_UNK1);
}
- if (data->cfg->type == sun8i_h3_phy) {
- if (phy->index == 0) {
- val = readl(data->base + REG_PHY_UNK_H3);
- writel(val & ~1, data->base + REG_PHY_UNK_H3);
- }
- } else {
- /* Enable USB 45 Ohm resistor calibration */
- if (phy->index == 0)
- sun4i_usb_phy_write(phy, PHY_RES45_CAL_EN, 0x01, 1);
+ /* Enable USB 45 Ohm resistor calibration */
+ if (phy->index == 0)
+ sun4i_usb_phy_write(phy, PHY_RES45_CAL_EN, 0x01, 1);
- /* Adjust PHY's magnitude and rate */
- sun4i_usb_phy_write(phy, PHY_TX_AMPLITUDE_TUNE, 0x14, 5);
+ /* Adjust PHY's magnitude and rate */
+ sun4i_usb_phy_write(phy, PHY_TX_AMPLITUDE_TUNE, 0x14, 5);
- /* Disconnect threshold adjustment */
- sun4i_usb_phy_write(phy, PHY_DISCON_TH_SEL,
- data->cfg->disc_thresh, 2);
- }
+ /* Disconnect threshold adjustment */
+ sun4i_usb_phy_write(phy, PHY_DISCON_TH_SEL,
+ data->cfg->disc_thresh, 2);
sun4i_usb_phy_passby(phy, 1);
@@ -484,6 +480,21 @@ static const struct phy_ops sun4i_usb_phy_ops = {
.owner = THIS_MODULE,
};
+static void sun4i_usb_phy0_reroute(struct sun4i_usb_phy_data *data, int id_det)
+{
+ u32 regval;
+
+ regval = readl(data->base + REG_PHY_OTGCTL);
+ if (id_det == 0) {
+ /* Host mode. Route phy0 to EHCI/OHCI */
+ regval &= ~OTGCTL_ROUTE_MUSB;
+ } else {
+ /* Peripheral mode. Route phy0 to MUSB */
+ regval |= OTGCTL_ROUTE_MUSB;
+ }
+ writel(regval, data->base + REG_PHY_OTGCTL);
+}
+
static void sun4i_usb_phy0_id_vbus_det_scan(struct work_struct *work)
{
struct sun4i_usb_phy_data *data =
@@ -544,6 +555,10 @@ static void sun4i_usb_phy0_id_vbus_det_scan(struct work_struct *work)
sun4i_usb_phy0_set_vbus_detect(phy0, 1);
mutex_unlock(&phy0->mutex);
}
+
+ /* Re-route PHY0 if necessary */
+ if (data->cfg->phy0_dual_route)
+ sun4i_usb_phy0_reroute(data, id_det);
}
if (vbus_notify)
@@ -698,7 +713,7 @@ static int sun4i_usb_phy_probe(struct platform_device *pdev)
return PTR_ERR(phy->reset);
}
- if (i) { /* No pmu for usbc0 */
+ if (i || data->cfg->phy0_dual_route) { /* No pmu for musb */
snprintf(name, sizeof(name), "pmu%d", i);
res = platform_get_resource_byname(pdev,
IORESOURCE_MEM, name);
@@ -824,6 +839,7 @@ static const struct sun4i_usb_phy_cfg sun8i_h3_cfg = {
.phyctl_offset = REG_PHYCTL_A33,
.dedicated_clocks = true,
.enable_pmu_unk1 = true,
+ .phy0_dual_route = true,
};
static const struct sun4i_usb_phy_cfg sun8i_v3s_cfg = {
--
2.11.0
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[GIT PULL] phy: for 4.12 Kishon Vijay Abraham I <kishon@ti.com> - 2017-04-10 15:20 +0200
[PATCH 02/32] phy: phy-exynos-pcie: make it explicitly non-modular Kishon Vijay Abraham I <kishon@ti.com> - 2017-04-10 15:20 +0200
[PATCH 08/32] phy: meson8b-usb2: fix offsets for some of the registers Kishon Vijay Abraham I <kishon@ti.com> - 2017-04-10 15:20 +0200
[PATCH 05/32] phy: sun4i-usb: change PHYCTL register clearing code Kishon Vijay Abraham I <kishon@ti.com> - 2017-04-10 15:20 +0200
[PATCH 04/32] dt: bindings: add pmu0 regs for USB PHYs on Allwinner H3/V3s/A64 Kishon Vijay Abraham I <kishon@ti.com> - 2017-04-10 15:20 +0200
[PATCH 20/32] phy: phy-mt65xx-usb3: add support for new version phy Kishon Vijay Abraham I <kishon@ti.com> - 2017-04-10 15:20 +0200
[PATCH 10/32] phy: exynos5: Remove duplicated defines of PHY register defines Kishon Vijay Abraham I <kishon@ti.com> - 2017-04-10 15:20 +0200
[PATCH 09/32] phy: exynos4: Remove duplicated defines of PHY register defines Kishon Vijay Abraham I <kishon@ti.com> - 2017-04-10 15:20 +0200
[PATCH 24/32] dt-bindings: add DT bindings for usb2-phy grf Kishon Vijay Abraham I <kishon@ti.com> - 2017-04-10 15:20 +0200
[PATCH 29/32] phy: qcom-qmp: new qmp phy driver for qcom-chipsets Kishon Vijay Abraham I <kishon@ti.com> - 2017-04-10 15:20 +0200
[PATCH 31/32] phy: rockchip-usb: Add vbus regulator support. Kishon Vijay Abraham I <kishon@ti.com> - 2017-04-10 15:30 +0200
[PATCH 27/32] phy: qcom-qusb2: New driver for QUSB2 PHY on Qcom chips Kishon Vijay Abraham I <kishon@ti.com> - 2017-04-10 15:30 +0200
[PATCH 15/32] phy: sun4i-usb: enable PHY0 dual route switching for A64 USB PHY Kishon Vijay Abraham I <kishon@ti.com> - 2017-04-10 15:30 +0200
[PATCH 13/32] phy: rockchip-inno-usb2: fix spelling mistake: "connecetd" -> "connected" Kishon Vijay Abraham I <kishon@ti.com> - 2017-04-10 15:30 +0200
[PATCH 03/32] mfd: exynos-lpass: Use common soc/exynos-regs-pmu.h header Kishon Vijay Abraham I <kishon@ti.com> - 2017-04-10 15:30 +0200
[PATCH 19/32] phy: phy-mt65xx-usb3: move clock from phy node into port nodes Kishon Vijay Abraham I <kishon@ti.com> - 2017-04-10 15:30 +0200
[PATCH 30/32] phy: bcm-ns-usb3: split all writes into reg & val pairs Kishon Vijay Abraham I <kishon@ti.com> - 2017-04-10 15:30 +0200
[PATCH 32/32] phy: qcom-qusb2: add NVMEM dependency Kishon Vijay Abraham I <kishon@ti.com> - 2017-04-10 15:30 +0200
[PATCH 17/32] phy: phy-mt65xx-usb3: increase LFPS filter threshold Kishon Vijay Abraham I <kishon@ti.com> - 2017-04-10 15:30 +0200
[PATCH 07/32] phy: sun4i-usb: support automatically switch PHY0 route to MUSB/HCI Kishon Vijay Abraham I <kishon@ti.com> - 2017-04-10 15:30 +0200
[PATCH 26/32] dt-bindings: phy: Add support for QUSB2 phy Kishon Vijay Abraham I <kishon@ti.com> - 2017-04-10 15:30 +0200
[PATCH 18/32] phy: phy-mt65xx-usb3: split SuperSpeed port into two ones Kishon Vijay Abraham I <kishon@ti.com> - 2017-04-10 15:30 +0200
[PATCH 14/32] phy: rcar-gen3-usb2: fix implementation for runtime PM Kishon Vijay Abraham I <kishon@ti.com> - 2017-04-10 15:30 +0200
[PATCH 06/32] phy: sun4i-usb: add PHYCTL offset for H3 SoC Kishon Vijay Abraham I <kishon@ti.com> - 2017-04-10 15:30 +0200
[PATCH 21/32] phy: phy-mt65xx-usb3: disable 100uA extraction from SS port to HS port Kishon Vijay Abraham I <kishon@ti.com> - 2017-04-10 15:30 +0200
[PATCH 28/32] dt-bindings: phy: Add support for QMP phy Kishon Vijay Abraham I <kishon@ti.com> - 2017-04-10 15:30 +0200
[PATCH 22/32] dt-bindings: phy-mt65xx-usb: add support for new version phy Kishon Vijay Abraham I <kishon@ti.com> - 2017-04-10 15:30 +0200
[PATCH 01/32] mfd: exynos-lpass: Use common soc/exynos-regs-pmu.h header Kishon Vijay Abraham I <kishon@ti.com> - 2017-04-10 15:30 +0200
Re: [PATCH 01/32] mfd: exynos-lpass: Use common soc/exynos-regs-pmu.h header Lee Jones <lee.jones@linaro.org> - 2017-04-11 16:20 +0200
Re: [PATCH 01/32] mfd: exynos-lpass: Use common soc/exynos-regs-pmu.h header Kishon Vijay Abraham I <kishon@ti.com> - 2017-04-11 16:30 +0200
Re: [PATCH 01/32] mfd: exynos-lpass: Use common soc/exynos-regs-pmu.h header Lee Jones <lee.jones@linaro.org> - 2017-04-11 18:40 +0200
Re: [PATCH 01/32] mfd: exynos-lpass: Use common soc/exynos-regs-pmu.h header Kishon Vijay Abraham I <kishon@ti.com> - 2017-04-12 07:30 +0200
Re: [PATCH 01/32] mfd: exynos-lpass: Use common soc/exynos-regs-pmu.h header Lee Jones <lee.jones@linaro.org> - 2017-04-12 10:00 +0200
Re: [PATCH 01/32] mfd: exynos-lpass: Use common soc/exynos-regs-pmu.h header Greg KH <gregkh@linuxfoundation.org> - 2017-04-11 16:30 +0200
[PATCH 25/32] phy: rockchip-inno-usb2: add support of usb2-phy for rk3328 Kishon Vijay Abraham I <kishon@TI.COM> - 2017-04-10 15:30 +0200
[PATCH 23/32] dt-bindings: phy-rockchip-inno-usb2: add assign clock property in usb2-phy node Kishon Vijay Abraham I <kishon@ti.com> - 2017-04-10 15:30 +0200
Re: [GIT PULL] phy: for 4.12 Greg KH <gregkh@linuxfoundation.org> - 2017-04-10 15:50 +0200
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