Re: [PATCH 1/3] perf/x86: add sysfs entry to freeze counter on SMI

From	Andi Kleen <ak@linux.intel.com>
Newsgroups	linux.kernel
Subject	Re: [PATCH 1/3] perf/x86: add sysfs entry to freeze counter on SMI
Date	2017-03-23 23:30 +0100
Message-ID	<tojp0-pl-9@gated-at.bofh.it> (permalink)
References	<tofOp-6a9-23@gated-at.bofh.it> <tofOq-6a9-27@gated-at.bofh.it> <tohGx-7w7-5@gated-at.bofh.it>
Organization	linux.* mail to news gateway

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On Thu, Mar 23, 2017 at 09:31:38PM +0100, Peter Zijlstra wrote:
> On Thu, Mar 23, 2017 at 11:25:49AM -0700, kan.liang@intel.com wrote:
> > From: Kan Liang <Kan.liang@intel.com>
> > 
> > When setting FREEZE_WHILE_SMM bit in IA32_DEBUGCTL, all performance
> > counters will be effected. There is no way to do per-counter freeze
> > on smi. So it should not use the per-event interface (e.g. ioctl or
> > event attribute) to set FREEZE_WHILE_SMM bit.
> > 
> > Adds sysfs entry /sys/device/cpu/freeze_on_smi to set FREEZE_WHILE_SMM
> > bit in IA32_DEBUGCTL. When set, freezes perfmon and trace messages
> > while in SMM.
> > Value has to be 0 or 1. It will be applied to all possible cpus.
> 
> So is there ever a good reason to not set this?

That means SMIs become invisible to most performance counters.

I don't think that's a good default. If the SMI takes 1% of my 
cycles I want to see it.

The masking trick is mainly useful when doing --smi-cost

-Andi

Thread

[PATCH 0/3]measure SMI cost kan.liang@intel.com - 2017-03-23 19:40 +0100
  [PATCH 1/3] perf/x86: add sysfs entry to freeze counter on SMI kan.liang@intel.com - 2017-03-23 19:40 +0100
    Re: [PATCH 1/3] perf/x86: add sysfs entry to freeze counter on SMI Peter Zijlstra <peterz@infradead.org> - 2017-03-23 21:40 +0100
      Re: [PATCH 1/3] perf/x86: add sysfs entry to freeze counter on SMI Thomas Gleixner <tglx@linutronix.de> - 2017-03-24 09:40 +0100
        RE: [PATCH 1/3] perf/x86: add sysfs entry to freeze counter on SMI "Liang, Kan" <kan.liang@intel.com> - 2017-03-24 15:20 +0100
          Re: [PATCH 1/3] perf/x86: add sysfs entry to freeze counter on SMI Peter Zijlstra <peterz@infradead.org> - 2017-03-24 15:30 +0100
    Re: [PATCH 1/3] perf/x86: add sysfs entry to freeze counter on SMI Peter Zijlstra <peterz@infradead.org> - 2017-03-23 21:40 +0100
      RE: [PATCH 1/3] perf/x86: add sysfs entry to freeze counter on SMI "Liang, Kan" <kan.liang@intel.com> - 2017-03-23 21:50 +0100
      Re: [PATCH 1/3] perf/x86: add sysfs entry to freeze counter on SMI Andi Kleen <ak@linux.intel.com> - 2017-03-23 23:30 +0100
        Re: [PATCH 1/3] perf/x86: add sysfs entry to freeze counter on SMI Peter Zijlstra <peterz@infradead.org> - 2017-03-24 09:20 +0100
  [PATCH 3/3] perf stat: Add support to measure SMI cost kan.liang@intel.com - 2017-03-23 19:40 +0100
  Re: [PATCH 0/3]measure SMI cost Thomas Gleixner <tglx@linutronix.de> - 2017-03-24 09:50 +0100
    Re: [PATCH 0/3]measure SMI cost Andi Kleen <ak@linux.intel.com> - 2017-03-24 12:50 +0100
      Re: [PATCH 0/3]measure SMI cost Thomas Gleixner <tglx@linutronix.de> - 2017-03-24 13:10 +0100
        RE: [PATCH 0/3]measure SMI cost "Liang, Kan" <kan.liang@intel.com> - 2017-03-24 15:20 +0100

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