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[PATCH v2 6/9] clk: meson: gxbb: mpll: use rw operation

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Use read/write operations for the mpll clocks instead of the
read-only ones.

Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
---
 drivers/clk/meson/gxbb.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/clk/meson/gxbb.c b/drivers/clk/meson/gxbb.c
index 79fb8989f8dd..5059c7bbdbb3 100644
--- a/drivers/clk/meson/gxbb.c
+++ b/drivers/clk/meson/gxbb.c
@@ -459,7 +459,7 @@ static struct meson_clk_mpll gxbb_mpll0 = {
 	.lock = &clk_lock,
 	.hw.init = &(struct clk_init_data){
 		.name = "mpll0",
-		.ops = &meson_clk_mpll_ro_ops,
+		.ops = &meson_clk_mpll_ops,
 		.parent_names = (const char *[]){ "fixed_pll" },
 		.num_parents = 1,
 	},
@@ -489,7 +489,7 @@ static struct meson_clk_mpll gxbb_mpll1 = {
 	.lock = &clk_lock,
 	.hw.init = &(struct clk_init_data){
 		.name = "mpll1",
-		.ops = &meson_clk_mpll_ro_ops,
+		.ops = &meson_clk_mpll_ops,
 		.parent_names = (const char *[]){ "fixed_pll" },
 		.num_parents = 1,
 	},
@@ -519,7 +519,7 @@ static struct meson_clk_mpll gxbb_mpll2 = {
 	.lock = &clk_lock,
 	.hw.init = &(struct clk_init_data){
 		.name = "mpll2",
-		.ops = &meson_clk_mpll_ro_ops,
+		.ops = &meson_clk_mpll_ops,
 		.parent_names = (const char *[]){ "fixed_pll" },
 		.num_parents = 1,
 	},
-- 
2.9.3

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[PATCH v2 0/9] clk: meson: update clock controller for audio support Jerome Brunet <jbrunet@baylibre.com> - 2017-03-09 11:50 +0100
  [PATCH v2 1/9] clk: meson: fix SET_PARM macro Jerome Brunet <jbrunet@baylibre.com> - 2017-03-09 11:50 +0100
  [PATCH v2 7/9] clk: meson8b: add the mplls clocks 0, 1 and 2 Jerome Brunet <jbrunet@baylibre.com> - 2017-03-09 12:00 +0100
  [PATCH v2 4/9] clk: gxbb: put dividers and muxes in tables Jerome Brunet <jbrunet@baylibre.com> - 2017-03-09 12:00 +0100
  [PATCH v2 5/9] clk: meson: mpll: add rw operation Jerome Brunet <jbrunet@baylibre.com> - 2017-03-09 12:00 +0100
  [PATCH v2 2/9] clk: meson: add missing const qualifiers on gate arrays Jerome Brunet <jbrunet@baylibre.com> - 2017-03-09 12:00 +0100
  [PATCH v2 6/9] clk: meson: gxbb: mpll: use rw operation Jerome Brunet <jbrunet@baylibre.com> - 2017-03-09 12:00 +0100
  [PATCH v2 8/9] clk: meson: mpll: correct N2 maximum value Jerome Brunet <jbrunet@baylibre.com> - 2017-03-09 12:00 +0100
  [PATCH v2 9/9] dt-bindings: clk: gxbb: expose i2s output clock gates Jerome Brunet <jbrunet@baylibre.com> - 2017-03-09 12:00 +0100
  [PATCH v2 3/9] clk: meson8b: put dividers and muxes in tables Jerome Brunet <jbrunet@baylibre.com> - 2017-03-09 12:00 +0100
  Re: [PATCH v2 0/9] clk: meson: update clock controller for audio support Kevin Hilman <khilman@baylibre.com> - 2017-03-11 01:40 +0100

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