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[PATCH v4 16/23] drm/rockchip: dw-mipi-dsi: properly configure PHY timing

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These values are specified as constant time periods but the PHY
configuration is in terms of the current lane byte clock so using
constant values guarantees that the timings will be outside the
specification with some display configurations.

Derive the necessary configuration from the byte clock in order to
ensure that the PHY configuration is correct.

Signed-off-by: John Keeping <john@metanate.com>
---
v4:
- Simplify ns2bc and ns2ui calculations as suggested by Sean Paul
v3:
- Wrap some long lines
Unchanged in v2
---
 drivers/gpu/drm/rockchip/dw-mipi-dsi.c | 35 ++++++++++++++++++++++++++++++----
 1 file changed, 31 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/rockchip/dw-mipi-dsi.c b/drivers/gpu/drm/rockchip/dw-mipi-dsi.c
index 4fee5176c606..9b6a60deb69e 100644
--- a/drivers/gpu/drm/rockchip/dw-mipi-dsi.c
+++ b/drivers/gpu/drm/rockchip/dw-mipi-dsi.c
@@ -383,6 +383,22 @@ static void dw_mipi_dsi_phy_write(struct dw_mipi_dsi *dsi, u8 test_code,
 	dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_TESTCLK | PHY_UNTESTCLR);
 }
 
+/**
+ * ns2bc - Nanoseconds to byte clock cycles
+ */
+static inline unsigned int ns2bc(struct dw_mipi_dsi *dsi, int ns)
+{
+	return DIV_ROUND_UP(ns * dsi->lane_mbps / 8, 1000);
+}
+
+/**
+ * ns2ui - Nanoseconds to UI time periods
+ */
+static inline unsigned int ns2ui(struct dw_mipi_dsi *dsi, int ns)
+{
+	return DIV_ROUND_UP(ns * dsi->lane_mbps, 1000);
+}
+
 static int dw_mipi_dsi_phy_init(struct dw_mipi_dsi *dsi)
 {
 	int ret, testdin, vco, val;
@@ -434,10 +450,21 @@ static int dw_mipi_dsi_phy_init(struct dw_mipi_dsi *dsi)
 					 SETRD_MAX | POWER_MANAGE |
 					 TER_RESISTORS_ON);
 
-
-	dw_mipi_dsi_phy_write(dsi, 0x70, TLP_PROGRAM_EN | 0xf);
-	dw_mipi_dsi_phy_write(dsi, 0x71, THS_PRE_PROGRAM_EN | 0x55);
-	dw_mipi_dsi_phy_write(dsi, 0x72, THS_ZERO_PROGRAM_EN | 0xa);
+	dw_mipi_dsi_phy_write(dsi, 0x60, TLP_PROGRAM_EN | ns2bc(dsi, 500));
+	dw_mipi_dsi_phy_write(dsi, 0x61, THS_PRE_PROGRAM_EN | ns2ui(dsi, 40));
+	dw_mipi_dsi_phy_write(dsi, 0x62, THS_ZERO_PROGRAM_EN | ns2bc(dsi, 300));
+	dw_mipi_dsi_phy_write(dsi, 0x63, THS_PRE_PROGRAM_EN | ns2ui(dsi, 100));
+	dw_mipi_dsi_phy_write(dsi, 0x64, BIT(5) | ns2bc(dsi, 100));
+	dw_mipi_dsi_phy_write(dsi, 0x65, BIT(5) | (ns2bc(dsi, 60) + 7));
+
+	dw_mipi_dsi_phy_write(dsi, 0x70, TLP_PROGRAM_EN | ns2bc(dsi, 500));
+	dw_mipi_dsi_phy_write(dsi, 0x71,
+			      THS_PRE_PROGRAM_EN | (ns2ui(dsi, 50) + 5));
+	dw_mipi_dsi_phy_write(dsi, 0x72,
+			      THS_ZERO_PROGRAM_EN | (ns2bc(dsi, 140) + 2));
+	dw_mipi_dsi_phy_write(dsi, 0x73,
+			      THS_PRE_PROGRAM_EN | (ns2ui(dsi, 60) + 8));
+	dw_mipi_dsi_phy_write(dsi, 0x74, BIT(5) | ns2bc(dsi, 100));
 
 	dsi_write(dsi, DSI_PHY_RSTZ, PHY_ENFORCEPLL | PHY_ENABLECLK |
 				     PHY_UNRSTZ | PHY_UNSHUTDOWNZ);
-- 
2.12.0.rc0.230.gf625d4cdb9.dirty

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[PATCH v4 00/23] drm/rockchip: MIPI fixes & improvements John Keeping <john@metanate.com> - 2017-02-24 14:00 +0100
  [PATCH v4 18/23] drm/rockchip: dw-mipi-dsi: use specific poll helper John Keeping <john@metanate.com> - 2017-02-24 14:00 +0100
  [PATCH v4 13/23] drm/rockchip: dw-mipi-dsi: fix escape clock rate John Keeping <john@metanate.com> - 2017-02-24 14:00 +0100
  [PATCH v4 23/23] drm/rockchip: dw-mipi-dsi: add reset control John Keeping <john@metanate.com> - 2017-02-24 14:00 +0100
  [PATCH v4 12/23] drm/rockchip: dw-mipi-dsi: allow commands in panel_disable John Keeping <john@metanate.com> - 2017-02-24 14:00 +0100
  [PATCH v4 02/23] drm/rockchip: dw-mipi-dsi: pass mode in where needed John Keeping <john@metanate.com> - 2017-02-24 14:00 +0100
  [PATCH v4 07/23] drm/rockchip: dw-mipi-dsi: include bad value in error message John Keeping <john@metanate.com> - 2017-02-24 14:00 +0100
  [PATCH v4 21/23] drm/rockchip: dw-mipi-dsi: defer probe if panel is not loaded John Keeping <john@metanate.com> - 2017-02-24 14:00 +0100
  [PATCH v4 19/23] drm/rockchip: dw-mipi-dsi: use positive check for N{H,V}SYNC John Keeping <john@metanate.com> - 2017-02-24 14:00 +0100
  [PATCH v4 06/23] drm/rockchip: dw-mipi-dsi: avoid out-of-bounds read on tx_buf John Keeping <john@metanate.com> - 2017-02-24 14:00 +0100
  [PATCH v4 15/23] drm/rockchip: dw-mipi-dsi: configure PHY before enabling John Keeping <john@metanate.com> - 2017-02-24 14:00 +0100
  [PATCH v4 08/23] drm/rockchip: dw-mipi-dsi: respect message flags John Keeping <john@metanate.com> - 2017-02-24 14:00 +0100
  [PATCH v4 04/23] drm/rockchip: dw-mipi-dsi: fix command header writes John Keeping <john@metanate.com> - 2017-02-24 14:00 +0100
  [PATCH v4 10/23] drm/rockchip: dw-mipi-dsi: don't assume buffer is aligned John Keeping <john@metanate.com> - 2017-02-24 14:00 +0100
  [PATCH v4 11/23] drm/rockchip: dw-mipi-dsi: prepare panel after phy init John Keeping <john@metanate.com> - 2017-02-24 14:00 +0100
  [PATCH v4 17/23] drm/rockchip: dw-mipi-dsi: improve PLL configuration John Keeping <john@metanate.com> - 2017-02-24 14:00 +0100
  [PATCH v4 09/23] drm/rockchip: dw-mipi-dsi: only request HS clock when required John Keeping <john@metanate.com> - 2017-02-24 14:00 +0100
  [PATCH v4 03/23] drm/rockchip: dw-mipi-dsi: remove mode_set hook John Keeping <john@metanate.com> - 2017-02-24 14:00 +0100
  [PATCH v4 05/23] drm/rockchip: dw-mipi-dsi: fix generic packet status check John Keeping <john@metanate.com> - 2017-02-24 14:00 +0100
  [PATCH v4 01/23] drm/rockchip: dw-mipi-dsi: don't configure hardware in mode_set for MIPI John Keeping <john@metanate.com> - 2017-02-24 14:00 +0100
  [PATCH v4 16/23] drm/rockchip: dw-mipi-dsi: properly configure PHY timing John Keeping <john@metanate.com> - 2017-02-24 14:00 +0100
  [PATCH v4 22/23] drm/rockchip: dw-mipi-dsi: support non-burst modes John Keeping <john@metanate.com> - 2017-02-24 14:10 +0100
  Re: [PATCH v4 00/23] drm/rockchip: MIPI fixes & improvements Mark yao <mark.yao@rock-chips.com> - 2017-02-27 02:50 +0100
  Re: [PATCH v4 00/23] drm/rockchip: MIPI fixes & improvements Chris Zhong <zyw@rock-chips.com> - 2017-02-27 04:40 +0100

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