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[PATCH 5/6] x86/asm/64: Drop __cacheline_aligned from struct x86_hw_tss

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Historically, the entire TSS + io bitmap structure was cacheline
aligned, but commit ca241c75037b ("x86: unify tss_struct") changed it
(presumably inadvertently) so that the fixed-layout hardware part is
cacheline-aligned and the io bitmap is after the padding.  This wastes
24 bytes (the hardware part should be 104 bytes, but this pads it to
128 bytes) and, serves no purpose, and causes sizeof(struct
x86_hw_tss) to have a confusing value.

Drop the pointless alignment.

Signed-off-by: Andy Lutomirski <luto@kernel.org>
---
 arch/x86/include/asm/processor.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/x86/include/asm/processor.h b/arch/x86/include/asm/processor.h
index feb2ab95b8f6..f385eca5407a 100644
--- a/arch/x86/include/asm/processor.h
+++ b/arch/x86/include/asm/processor.h
@@ -304,7 +304,7 @@ struct x86_hw_tss {
 	u16			reserved5;
 	u16			io_bitmap_base;
 
-} __attribute__((packed)) ____cacheline_aligned;
+} __attribute__((packed));
 #endif
 
 /*
-- 
2.9.3

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[PATCH 0/6] KVM TSS cleanups and speedups Andy Lutomirski <luto@kernel.org> - 2017-02-20 18:00 +0100
  [PATCH 2/6] x86/kvm/vmx: Don't fetch the TSS base from the GDT Andy Lutomirski <luto@kernel.org> - 2017-02-20 18:00 +0100
  [PATCH 5/6] x86/asm/64: Drop __cacheline_aligned from struct x86_hw_tss Andy Lutomirski <luto@kernel.org> - 2017-02-20 18:00 +0100
  [PATCH 1/6] x86/asm: Define the kernel TSS limit in a macro Andy Lutomirski <luto@kernel.org> - 2017-02-20 18:10 +0100
  Re: [PATCH 0/6] KVM TSS cleanups and speedups Paolo Bonzini <pbonzini@redhat.com> - 2017-02-20 19:00 +0100

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