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Re: [PATCH 9/9] RISC-V: Build Infastructure

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On Wed, Jun 28, 2017 at 11:55:38AM -0700, Palmer Dabbelt wrote:
> diff --git a/arch/riscv/kernel/Makefile b/arch/riscv/kernel/Makefile
> new file mode 100644
> index 000000000000..7f58cd251ab8
> --- /dev/null
> +++ b/arch/riscv/kernel/Makefile
> @@ -0,0 +1,16 @@
> +#
> +# Makefile for the RISC-V Linux kernel
> +#
> +
> +extra-y := head.o vmlinux.lds
> +
> +obj-y	:= cpu.o entry.o irq.o process.o ptrace.o reset.o setup.o \
> +	   signal.o syscall_table.o sys_riscv.o time.o traps.o \
> +	   riscv_ksyms.o stacktrace.o vdso.o cacheinfo.o vdso/

I would suggest splitting these sort of things onto separate lines.
It'll make later changes much more readable (especially when you're
escaping newlines) as well as avoiding conflicts.

> +
> +CFLAGS_setup.o := -mcmodel=medany
> +
> +obj-$(CONFIG_SMP)		+= smpboot.o smp.o

same here

> +obj-$(CONFIG_MODULES)		+= module.o
> +
> +clean:

> diff --git a/arch/riscv/lib/Makefile b/arch/riscv/lib/Makefile
> new file mode 100644
> index 000000000000..120c38e77a46
> --- /dev/null
> +++ b/arch/riscv/lib/Makefile
> @@ -0,0 +1,5 @@
> +lib-y	:= delay.o memcpy.o memset.o uaccess.o

and here

> +
> +ifeq ($(CONFIG_64BIT),)
> +lib-y += udivdi3.o
> +endif

Would this work?

lib-$(CONFIG_32BIT) += udivdi3.o

> diff --git a/arch/riscv/mm/Makefile b/arch/riscv/mm/Makefile
> new file mode 100644
> index 000000000000..36ebe6feb5d6
> --- /dev/null
> +++ b/arch/riscv/mm/Makefile
> @@ -0,0 +1 @@
> +obj-y := init.o fault.o extable.o ioremap.o

and here

Cheers
James

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RISC-V Linux Port v3 Palmer Dabbelt <palmer@dabbelt.com> - 2017-06-28 21:00 +0200
  [PATCH 6/9] RISC-V: Device, timer, IRQs, and the SBI Palmer Dabbelt <palmer@dabbelt.com> - 2017-06-28 21:00 +0200
    Re: [PATCH 6/9] RISC-V: Device, timer, IRQs, and the SBI Tobias Klauser <tklauser@distanz.ch> - 2017-06-29 10:40 +0200
      Re: [PATCH 6/9] RISC-V: Device, timer, IRQs, and the SBI Palmer Dabbelt <palmer@dabbelt.com> - 2017-06-30 01:00 +0200
        Re: [PATCH 6/9] RISC-V: Device, timer, IRQs, and the SBI Tobias Klauser <tklauser@distanz.ch> - 2017-06-30 10:00 +0200
  [PATCH 4/9] RISC-V: ELF and module implementation Palmer Dabbelt <palmer@dabbelt.com> - 2017-06-28 21:00 +0200
  [PATCH 7/9] RISC-V: Paging and MMU Palmer Dabbelt <palmer@dabbelt.com> - 2017-06-28 21:10 +0200
    Re: [PATCH 7/9] RISC-V: Paging and MMU James Hogan <james.hogan@imgtec.com> - 2017-06-29 01:20 +0200
      Re: [PATCH 7/9] RISC-V: Paging and MMU Palmer Dabbelt <palmer@dabbelt.com> - 2017-06-30 00:20 +0200
  [PATCH 9/9] RISC-V: Build Infastructure Palmer Dabbelt <palmer@dabbelt.com> - 2017-06-28 21:10 +0200
    Re: [PATCH 9/9] RISC-V: Build Infastructure Karsten Merker <merker@debian.org> - 2017-06-28 23:10 +0200
      Re: [PATCH 9/9] RISC-V: Build Infastructure Palmer Dabbelt <palmer@dabbelt.com> - 2017-06-28 23:20 +0200
    Re: [PATCH 9/9] RISC-V: Build Infastructure James Hogan <james.hogan@imgtec.com> - 2017-06-28 23:30 +0200
      Re: [PATCH 9/9] RISC-V: Build Infastructure Palmer Dabbelt <palmer@dabbelt.com> - 2017-06-29 18:40 +0200
    Re: [PATCH 9/9] RISC-V: Build Infastructure James Hogan <james.hogan@imgtec.com> - 2017-06-29 01:00 +0200
      Re: [PATCH 9/9] RISC-V: Build Infastructure Palmer Dabbelt <palmer@dabbelt.com> - 2017-06-30 00:20 +0200
  Re: [PATCH 8/9] RISC-V: User-facing API Thomas Gleixner <tglx@linutronix.de> - 2017-06-29 00:00 +0200
  Re: [PATCH 8/9] RISC-V: User-facing API Thomas Gleixner <tglx@linutronix.de> - 2017-06-29 00:00 +0200
    Re: [PATCH 8/9] RISC-V: User-facing API Palmer Dabbelt <palmer@dabbelt.com> - 2017-06-29 19:30 +0200
  Re: [PATCH 8/9] RISC-V: User-facing API James Hogan <james.hogan@imgtec.com> - 2017-06-29 00:50 +0200
    Re: [PATCH 8/9] RISC-V: User-facing API Palmer Dabbelt <palmer@dabbelt.com> - 2017-06-29 23:50 +0200
  Re: [PATCH 5/9] RISC-V: Task implementation James Hogan <james.hogan@imgtec.com> - 2017-06-29 01:40 +0200
    Re: [PATCH 5/9] RISC-V: Task implementation Palmer Dabbelt <palmer@dabbelt.com> - 2017-06-30 01:00 +0200
  Re: [PATCH 5/9] RISC-V: Task implementation Tobias Klauser <tklauser@distanz.ch> - 2017-06-29 10:30 +0200
    Re: [PATCH 5/9] RISC-V: Task implementation Palmer Dabbelt <palmer@dabbelt.com> - 2017-06-30 01:00 +0200
  Re: [PATCH 1/9] RISC-V: Init and Halt Code Geert Uytterhoeven <geert@linux-m68k.org> - 2017-06-29 11:50 +0200
    Re: [PATCH 1/9] RISC-V: Init and Halt Code Palmer Dabbelt <palmer@dabbelt.com> - 2017-06-30 01:00 +0200

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