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[RESEND PATCH] MIPS: head: Reorder instructions missing a delay slot

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In this sequence the 'move' is assumed in the delay slot of the 'beq',
but head.S is in reorder mode and the former gets pushed one 'nop'
farther by the assembler.

The corrected behavior made booting with an UHI supplied dtb erratic.

Fixes: 15f37e158892 ("MIPS: store the appended dtb address in a variable")
Cc: <stable@vger.kernel.org>
Cc: Ralf Baechle <ralf@linux-mips.org>
Cc: Jonas Gorski <jogo@openwrt.org>
Signed-off-by: Karl Beldan <karl.beldan+oss@gmail.com>
---
 arch/mips/kernel/head.S | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/mips/kernel/head.S b/arch/mips/kernel/head.S
index cf05220..d1bb506 100644
--- a/arch/mips/kernel/head.S
+++ b/arch/mips/kernel/head.S
@@ -106,8 +106,8 @@ NESTED(kernel_entry, 16, sp)			# kernel entry point
 	beq		t0, t1, dtb_found
 #endif
 	li		t1, -2
-	beq		a0, t1, dtb_found
 	move		t2, a1
+	beq		a0, t1, dtb_found
 
 	li		t2, 0
 dtb_found:
-- 
2.10.1

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[RESEND PATCH] MIPS: head: Reorder instructions missing a delay slot Karl Beldan <karl.beldan@gmail.com> - 2017-06-27 21:30 +0200
  Re: [RESEND PATCH] MIPS: head: Reorder instructions missing a delay  slot James Hogan <james.hogan@imgtec.com> - 2017-06-27 22:40 +0200
  Re: [RESEND PATCH] MIPS: head: Reorder instructions missing a delay  slot Ralf Baechle <ralf@linux-mips.org> - 2017-06-27 23:50 +0200

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