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Groups > linux.kernel > #1675477
| From | Varadarajan Narayanan <varada@codeaurora.org> |
|---|---|
| Newsgroups | linux.kernel |
| Subject | [PATCH v4 14/14] spi: qup: Ensure done detection |
| Date | 2017-06-27 11:50 +0200 |
| Message-ID | <tWVib-739-47@gated-at.bofh.it> (permalink) |
| References | <tWVi9-739-11@gated-at.bofh.it> |
| Organization | linux.* mail to news gateway |
This patch fixes an issue where a SPI transaction has completed, but the
done condition is missed. This occurs because at the time of interrupt the
MAX_INPUT_DONE_FLAG is not asserted. However, in the process of reading
blocks of data from the FIFO, the last portion of data comes in.
The opflags read at the beginning of the irq handler no longer matches the
current opflag state. To get around this condition, the block read
function should update the opflags so that done detection is correct after
the return.
Signed-off-by: Andy Gross <agross@codeaurora.org>
Signed-off-by: Abhishek Sahu <absahu@codeaurora.org>
Signed-off-by: Varadarajan Narayanan <varada@codeaurora.org>
---
drivers/spi/spi-qup.c | 12 +++++++-----
1 file changed, 7 insertions(+), 5 deletions(-)
diff --git a/drivers/spi/spi-qup.c b/drivers/spi/spi-qup.c
index a39a0d2..ca5206e 100644
--- a/drivers/spi/spi-qup.c
+++ b/drivers/spi/spi-qup.c
@@ -268,7 +268,7 @@ static void spi_qup_read_from_fifo(struct spi_qup *controller, u32 num_words)
}
}
-static void spi_qup_read(struct spi_qup *controller)
+static void spi_qup_read(struct spi_qup *controller, u32 *opflags)
{
u32 remainder, words_per_block, num_words;
bool is_block_mode = controller->mode == QUP_IO_M_MODE_BLOCK;
@@ -307,10 +307,12 @@ static void spi_qup_read(struct spi_qup *controller)
/*
* Due to extra stickiness of the QUP_OP_IN_SERVICE_FLAG during block
- * mode reads, it has to be cleared again at the very end
+ * reads, it has to be cleared again at the very end. However, be sure
+ * to refresh opflags value because MAX_INPUT_DONE_FLAG may now be
+ * present and this is used to determine if transaction is complete
*/
- if (is_block_mode && spi_qup_is_flag_set(controller,
- QUP_OP_MAX_INPUT_DONE_FLAG))
+ *opflags = readl_relaxed(controller->base + QUP_OPERATIONAL);
+ if (is_block_mode && *opflags & QUP_OP_MAX_INPUT_DONE_FLAG)
writel_relaxed(QUP_OP_IN_SERVICE_FLAG,
controller->base + QUP_OPERATIONAL);
@@ -617,7 +619,7 @@ static irqreturn_t spi_qup_qup_irq(int irq, void *dev_id)
writel_relaxed(opflags, controller->base + QUP_OPERATIONAL);
} else {
if (opflags & QUP_OP_IN_SERVICE_FLAG)
- spi_qup_read(controller);
+ spi_qup_read(controller, &opflags);
if (opflags & QUP_OP_OUT_SERVICE_FLAG)
spi_qup_write(controller);
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
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[PATCH v4 00/14] spi: qup: Fixes and add support for >64k transfers Varadarajan Narayanan <varada@codeaurora.org> - 2017-06-27 11:50 +0200 [PATCH v4 07/14] spi: qup: Fix transaction done signaling Varadarajan Narayanan <varada@codeaurora.org> - 2017-06-27 11:50 +0200 [PATCH v4 11/14] spi: qup: allow block mode to generate multiple transactions Varadarajan Narayanan <varada@codeaurora.org> - 2017-06-27 11:50 +0200 [PATCH v4 14/14] spi: qup: Ensure done detection Varadarajan Narayanan <varada@codeaurora.org> - 2017-06-27 11:50 +0200 [PATCH v4 03/14] spi: qup: Add completion structures for DMA Varadarajan Narayanan <varada@codeaurora.org> - 2017-06-27 11:50 +0200 [PATCH v4 08/14] spi: qup: Do block sized read/write in block mode Varadarajan Narayanan <varada@codeaurora.org> - 2017-06-27 11:50 +0200 [PATCH v4 02/14] spi: qup: Setup DMA mode correctly Varadarajan Narayanan <varada@codeaurora.org> - 2017-06-27 11:50 +0200 [PATCH v4 12/14] spi: qup: refactor spi_qup_prep_sg Varadarajan Narayanan <varada@codeaurora.org> - 2017-06-27 11:50 +0200 [PATCH v4 01/14] spi: qup: Enable chip select support Varadarajan Narayanan <varada@codeaurora.org> - 2017-06-27 12:00 +0200 [PATCH v4 05/14] spi: qup: Place the QUP in run mode before DMA Varadarajan Narayanan <varada@codeaurora.org> - 2017-06-27 12:00 +0200
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