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Groups > linux.kernel > #1673251
| From | Zhi Mao <zhi.mao@mediatek.com> |
|---|---|
| Newsgroups | linux.kernel |
| Subject | [PATCH v2 2/6] pwm: mediatek: fix pwm source clock selection |
| Date | 2017-06-23 07:10 +0200 |
| Message-ID | <tVp0Z-6lw-5@gated-at.bofh.it> (permalink) |
| References | <tVp0Z-6lw-7@gated-at.bofh.it> |
| Organization | linux.* mail to news gateway |
In original code, the pwm output frequency is not correct when set bit<3>=1 to PWMCON register. Signed-off-by: Zhi Mao <zhi.mao@mediatek.com> --- drivers/pwm/pwm-mediatek.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/pwm/pwm-mediatek.c b/drivers/pwm/pwm-mediatek.c index 5c11bc7..d08b5b3 100644 --- a/drivers/pwm/pwm-mediatek.c +++ b/drivers/pwm/pwm-mediatek.c @@ -91,7 +91,7 @@ static int mtk_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm, if (clkdiv > 7) return -EINVAL; - mtk_pwm_writel(pc, pwm->hwpwm, PWMCON, BIT(15) | BIT(3) | clkdiv); + mtk_pwm_writel(pc, pwm->hwpwm, PWMCON, BIT(15) | clkdiv); mtk_pwm_writel(pc, pwm->hwpwm, PWMDWIDTH, period_ns / resolution); mtk_pwm_writel(pc, pwm->hwpwm, PWMTHRES, duty_ns / resolution); -- 1.7.9.5
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[PATCH v2 2/6] pwm: mediatek: fix pwm source clock selection Zhi Mao <zhi.mao@mediatek.com> - 2017-06-23 07:10 +0200
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