Re: [PATCH 2/3] x86/apic: Add TSC_DEADLINE quirk due to errata

From	Thomas Gleixner <tglx@linutronix.de>
Newsgroups	linux.kernel
Subject	Re: [PATCH 2/3] x86/apic: Add TSC_DEADLINE quirk due to errata
Date	2017-06-01 12:00 +0200
Message-ID	<tNv3A-Uw-7@gated-at.bofh.it> (permalink)
References	<tNecp-6Ly-5@gated-at.bofh.it> <tNecq-6Ly-31@gated-at.bofh.it> <tNjOO-28K-45@gated-at.bofh.it> <tNuKe-LA-25@gated-at.bofh.it>
Organization	linux.* mail to news gateway

Show all headers | View raw

On Thu, 1 Jun 2017, Peter Zijlstra wrote:
> That commit also states that is avoids a superfluous microcode load. And
> we've verified on affected systems (both Thomas and I have a SKL system
> with the PRMRR bit set in MTRRCAP) that when we manually load the
> microcode image the reported revision number matches the one from the
> image.
> 
>  [    0.000000] microcode: microcode updated early to revision 0xba, date = 2017-04-09
>  [    2.297894] microcode: sig=0x506e3, pf=0x2, revision=0xba
> 
> And:
> 
> # hexdump /lib/firmware/intel-ucode/06-5e-03 | head -1
> 0000000 0001 0000 00ba 0000 2017 0409 06e3 0005
>                   ^^^^^^^^^
> 
> So aside from a possible OS re-load of the microcode, the issue doesn't
> appear to have any negative effect.
> 
> 
> The microcode people (Cc'ed) might want to further look into this is
> they care about avoiding the superfluous reload, but for the purpose of
> this patch all is well.

Avoiding the superflous reload is dangerous. If the BIOS/FIT nonsense gets
fixed (however unlikely that is) then we run into an even worse problem
because then the kernel will not load version 5 if the CPU says version 4.
That's way worse than reloading the same version for nothing.

Thanks,

	tglx

Thread

[PATCH 0/3] x86: TSC_DEADLINE vs TSC_ADJUST and microcode revisions Peter Zijlstra <peterz@infradead.org> - 2017-05-31 18:00 +0200
  [PATCH 1/3] x86/apic: Change the lapic name in deadline mode Peter Zijlstra <peterz@infradead.org> - 2017-05-31 18:00 +0200
    [tip:x86/timers] x86/apic: Change the lapic name in deadline mode tip-bot for Peter Zijlstra <tipbot@zytor.com> - 2017-06-04 22:10 +0200
  [PATCH 2/3] x86/apic: Add TSC_DEADLINE quirk due to errata Peter Zijlstra <peterz@infradead.org> - 2017-05-31 18:00 +0200
    Re: [PATCH 2/3] x86/apic: Add TSC_DEADLINE quirk due to errata Henrique de Moraes Holschuh <hmh@hmh.eng.br> - 2017-06-01 00:00 +0200
      Re: [PATCH 2/3] x86/apic: Add TSC_DEADLINE quirk due to errata Peter Zijlstra <peterz@infradead.org> - 2017-06-01 11:40 +0200
        Re: [PATCH 2/3] x86/apic: Add TSC_DEADLINE quirk due to errata Thomas Gleixner <tglx@linutronix.de> - 2017-06-01 12:00 +0200
        Re: [PATCH 2/3] x86/apic: Add TSC_DEADLINE quirk due to errata Henrique de Moraes Holschuh <hmh@hmh.eng.br> - 2017-06-01 19:30 +0200
    [tip:x86/timers] x86/apic: Add TSC_DEADLINE quirk due to errata tip-bot for Peter Zijlstra <tipbot@zytor.com> - 2017-06-04 22:10 +0200
  [PATCH 3/3] x86/tsc: Remove the TSC_ADJUST clamp Peter Zijlstra <peterz@infradead.org> - 2017-05-31 18:00 +0200
    [tip:x86/timers] x86/tsc: Remove the TSC_ADJUST clamp tip-bot for Peter Zijlstra <tipbot@zytor.com> - 2017-06-04 22:10 +0200
  Re: [PATCH 0/3] x86: TSC_DEADLINE vs TSC_ADJUST and microcode  revisions Henrique de Moraes Holschuh <hmh@hmh.eng.br> - 2017-05-31 20:40 +0200

csiph-web