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Groups > linux.kernel > #1654666
| From | Henrique de Moraes Holschuh <hmh@hmh.eng.br> |
|---|---|
| Newsgroups | linux.kernel |
| Subject | Re: [PATCH 2/3] x86/apic: Add TSC_DEADLINE quirk due to errata |
| Date | 2017-06-01 00:00 +0200 |
| Message-ID | <tNjOO-28K-45@gated-at.bofh.it> (permalink) |
| References | <tNecp-6Ly-5@gated-at.bofh.it> <tNecq-6Ly-31@gated-at.bofh.it> |
| Organization | linux.* mail to news gateway |
On Wed, 31 May 2017, Peter Zijlstra wrote: > + DEADLINE_MODEL_MATCH_REV ( INTEL_FAM6_SKYLAKE_X, 0x02000014), ... > + DEADLINE_MODEL_MATCH_REV ( INTEL_FAM6_SKYLAKE_MOBILE, 0xb2), > + DEADLINE_MODEL_MATCH_REV ( INTEL_FAM6_SKYLAKE_DESKTOP, 0xb2), ... > + DEADLINE_MODEL_MATCH_REV ( INTEL_FAM6_KABYLAKE_MOBILE, 0x52), > + DEADLINE_MODEL_MATCH_REV ( INTEL_FAM6_KABYLAKE_DESKTOP, 0x52), Maybe these revisions need to be decreased by one, so that the SGX behavior of messing with the microcode revision is taken into account? When the processor microcode is auto-updated from the (signed) FIT, and SGX's PRMRR feature is supported, the processor will report its microcode revision as one less. Therefore, a microcode update with revision 0xb2 auto-loaded from FIT would be reported by RDMSR(0x8b) as revision 0xb1. I know about this SGX-related behavior from a coreboot commit from ~two years ago (link below). As far as I can tell, the Intel 64/IA32 SDM is *still* missing any mention about this behavior in vol 3A section 9.11 (where it describes microcode updates). https://review.coreboot.org/cgit/coreboot.git/commit/?id=5042aad4ded1651638ae9b60e34114b65e4f211e -- Henrique Holschuh
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[PATCH 0/3] x86: TSC_DEADLINE vs TSC_ADJUST and microcode revisions Peter Zijlstra <peterz@infradead.org> - 2017-05-31 18:00 +0200
[PATCH 1/3] x86/apic: Change the lapic name in deadline mode Peter Zijlstra <peterz@infradead.org> - 2017-05-31 18:00 +0200
[tip:x86/timers] x86/apic: Change the lapic name in deadline mode tip-bot for Peter Zijlstra <tipbot@zytor.com> - 2017-06-04 22:10 +0200
[PATCH 2/3] x86/apic: Add TSC_DEADLINE quirk due to errata Peter Zijlstra <peterz@infradead.org> - 2017-05-31 18:00 +0200
Re: [PATCH 2/3] x86/apic: Add TSC_DEADLINE quirk due to errata Henrique de Moraes Holschuh <hmh@hmh.eng.br> - 2017-06-01 00:00 +0200
Re: [PATCH 2/3] x86/apic: Add TSC_DEADLINE quirk due to errata Peter Zijlstra <peterz@infradead.org> - 2017-06-01 11:40 +0200
Re: [PATCH 2/3] x86/apic: Add TSC_DEADLINE quirk due to errata Thomas Gleixner <tglx@linutronix.de> - 2017-06-01 12:00 +0200
Re: [PATCH 2/3] x86/apic: Add TSC_DEADLINE quirk due to errata Henrique de Moraes Holschuh <hmh@hmh.eng.br> - 2017-06-01 19:30 +0200
[tip:x86/timers] x86/apic: Add TSC_DEADLINE quirk due to errata tip-bot for Peter Zijlstra <tipbot@zytor.com> - 2017-06-04 22:10 +0200
[PATCH 3/3] x86/tsc: Remove the TSC_ADJUST clamp Peter Zijlstra <peterz@infradead.org> - 2017-05-31 18:00 +0200
[tip:x86/timers] x86/tsc: Remove the TSC_ADJUST clamp tip-bot for Peter Zijlstra <tipbot@zytor.com> - 2017-06-04 22:10 +0200
Re: [PATCH 0/3] x86: TSC_DEADLINE vs TSC_ADJUST and microcode revisions Henrique de Moraes Holschuh <hmh@hmh.eng.br> - 2017-05-31 20:40 +0200
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