Re: [v5 1/4] ACPICA: IORT: Add Cavium ThunderX2 SMMUv3 model definition.

From	"Rafael J. Wysocki" <rjw@rjwysocki.net>
Newsgroups	linux.kernel
Subject	Re: [v5 1/4] ACPICA: IORT: Add Cavium ThunderX2 SMMUv3 model definition.
Date	2017-05-11 02:40 +0200
Message-ID	<tFKj7-7BT-1@gated-at.bofh.it> (permalink)
References	<tFKj7-7BT-3@gated-at.bofh.it> <tFKj7-7BT-5@gated-at.bofh.it>
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On Wednesday, May 10, 2017 05:01:55 PM Geetha sowjanya wrote:
> From: Linu Cherian <linu.cherian@cavium.com>
> 
> Add SMMUv3 model definition for ThunderX2.
> 
> Signed-off-by: Linu Cherian <linu.cherian@cavium.com>
> Signed-off-by: Geetha Sowjanya <geethasowjanya.akula@cavium.com>

This is an ACPICA change, but you have not included the ACPICA maintainers
into your original CC list (added now).

Bob, Lv, how should this be routed?

Do you want to apply this patch upstream first or can we make this change in
Linux and upstream in parallel?  That shouldn't be a big deal, right?

> ---
>  include/acpi/actbl2.h | 2 ++
>  1 file changed, 2 insertions(+)
> 
> diff --git a/include/acpi/actbl2.h b/include/acpi/actbl2.h
> index faa9f2c..76a6f5d 100644
> --- a/include/acpi/actbl2.h
> +++ b/include/acpi/actbl2.h
> @@ -779,6 +779,8 @@ struct acpi_iort_smmu {
>  #define ACPI_IORT_SMMU_CORELINK_MMU400  0x00000002	/* ARM Corelink MMU-400 */
>  #define ACPI_IORT_SMMU_CORELINK_MMU500  0x00000003	/* ARM Corelink MMU-500 */
>  
> +#define ACPI_IORT_SMMU_V3_CAVIUM_CN99XX 0x00000002 /* Cavium ThunderX2 SMMUv3 */
> +
>  /* Masks for Flags field above */
>  
>  #define ACPI_IORT_SMMU_DVM_SUPPORTED    (1)
> 

Thanks,
Rafael

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Re: [v5 1/4] ACPICA: IORT: Add Cavium ThunderX2 SMMUv3 model definition. "Rafael J. Wysocki" <rjw@rjwysocki.net> - 2017-05-11 02:40 +0200
  Re: [v5 1/4] ACPICA: IORT: Add Cavium ThunderX2 SMMUv3 model  definition. Will Deacon <will.deacon@arm.com> - 2017-05-11 10:50 +0200
    Re: [v5 1/4] ACPICA: IORT: Add Cavium ThunderX2 SMMUv3 model definition. "Rafael J. Wysocki" <rjw@rjwysocki.net> - 2017-05-11 16:50 +0200

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