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[PATCH v7 13/26] x86/insn-eval: Add function to get default params of code segment

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This function returns the default values of the address and operand sizes
as specified in the segment descriptor. This information is determined
from the D and L bits. Hence, it can be used for both IA-32e 64-bit and
32-bit legacy modes. For virtual-8086 mode, the default address and
operand sizes are always 2 bytes.

The D bit is only meaningful for code segments. Thus, these functions
always use the code segment selector contained in regs.

Cc: Dave Hansen <dave.hansen@linux.intel.com>
Cc: Adam Buchbinder <adam.buchbinder@gmail.com>
Cc: Colin Ian King <colin.king@canonical.com>
Cc: Lorenzo Stoakes <lstoakes@gmail.com>
Cc: Qiaowei Ren <qiaowei.ren@intel.com>
Cc: Arnaldo Carvalho de Melo <acme@redhat.com>
Cc: Masami Hiramatsu <mhiramat@kernel.org>
Cc: Adrian Hunter <adrian.hunter@intel.com>
Cc: Kees Cook <keescook@chromium.org>
Cc: Thomas Garnier <thgarnie@google.com>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Borislav Petkov <bp@suse.de>
Cc: Dmitry Vyukov <dvyukov@google.com>
Cc: Ravi V. Shankar <ravi.v.shankar@intel.com>
Cc: x86@kernel.org
Signed-off-by: Ricardo Neri <ricardo.neri-calderon@linux.intel.com>
---
 arch/x86/include/asm/insn-eval.h |  6 ++++
 arch/x86/lib/insn-eval.c         | 65 ++++++++++++++++++++++++++++++++++++++++
 2 files changed, 71 insertions(+)

diff --git a/arch/x86/include/asm/insn-eval.h b/arch/x86/include/asm/insn-eval.h
index 7f3c7fe..9ed1c88 100644
--- a/arch/x86/include/asm/insn-eval.h
+++ b/arch/x86/include/asm/insn-eval.h
@@ -11,9 +11,15 @@
 #include <linux/err.h>
 #include <asm/ptrace.h>
 
+struct insn_code_seg_defaults {
+	unsigned char address_bytes;
+	unsigned char operand_bytes;
+};
+
 void __user *insn_get_addr_ref(struct insn *insn, struct pt_regs *regs);
 int insn_get_modrm_rm_off(struct insn *insn, struct pt_regs *regs);
 unsigned long insn_get_seg_base(struct pt_regs *regs, struct insn *insn,
 				int regoff);
+struct insn_code_seg_defaults insn_get_code_seg_defaults(struct pt_regs *regs);
 
 #endif /* _ASM_X86_INSN_EVAL_H */
diff --git a/arch/x86/lib/insn-eval.c b/arch/x86/lib/insn-eval.c
index c77ed80..693e5a8 100644
--- a/arch/x86/lib/insn-eval.c
+++ b/arch/x86/lib/insn-eval.c
@@ -603,6 +603,71 @@ static unsigned long get_seg_limit(struct pt_regs *regs, struct insn *insn,
 }
 
 /**
+ * insn_get_code_seg_defaults() - Obtain code segment default parameters
+ * @regs:	Structure with register values as seen when entering kernel mode
+ *
+ * Obtain the default parameters of the code segment: address and operand sizes.
+ * The code segment is obtained from the selector contained in the CS register
+ * in regs. In protected mode, the default address is determined by inspecting
+ * the L and D bits of the segment descriptor. In virtual-8086 mode, the default
+ * is always two bytes for both address and operand sizes.
+ *
+ * Return: A populated insn_code_seg_defaults structure on success. The
+ * structure contains only zeros on failure.
+ */
+struct insn_code_seg_defaults insn_get_code_seg_defaults(struct pt_regs *regs)
+{
+	struct desc_struct *desc;
+	struct insn_code_seg_defaults defs;
+	unsigned short sel;
+	/*
+	 * The most significant byte of AR_TYPE_MASK determines whether a
+	 * segment contains data or code.
+	 */
+	unsigned int type_mask = AR_TYPE_MASK & (1 << 11);
+
+	memset(&defs, 0, sizeof(defs));
+
+	if (v8086_mode(regs)) {
+		defs.address_bytes = 2;
+		defs.operand_bytes = 2;
+		return defs;
+	}
+
+	sel = (unsigned short)regs->cs;
+
+	desc = get_desc(sel);
+	if (!desc)
+		return defs;
+
+	/* if data segment, return */
+	if (!(desc->b & type_mask))
+		return defs;
+
+	switch ((desc->l << 1) | desc->d) {
+	case 0: /* Legacy mode. CS.L=0, CS.D=0 */
+		defs.address_bytes = 2;
+		defs.operand_bytes = 2;
+		break;
+	case 1: /* Legacy mode. CS.L=0, CS.D=1 */
+		defs.address_bytes = 4;
+		defs.operand_bytes = 4;
+		break;
+	case 2: /* IA-32e 64-bit mode. CS.L=1, CS.D=0 */
+		defs.address_bytes = 8;
+		defs.operand_bytes = 4;
+		break;
+	case 3: /* Invalid setting. CS.L=1, CS.D=1 */
+		/* fall through */
+	default:
+		defs.address_bytes = 0;
+		defs.operand_bytes = 0;
+	}
+
+	return defs;
+}
+
+/**
  * insn_get_reg_offset_modrm_rm() - Obtain register in r/m part of ModRM byte
  * @insn:	Instruction structure containing the ModRM byte
  * @regs:	Structure with register values as seen when entering kernel mode
-- 
2.9.3

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[PATCH v7 00/26] x86: Enable User-Mode Instruction Prevention Ricardo Neri <ricardo.neri-calderon@linux.intel.com> - 2017-05-05 20:20 +0200
  [PATCH v7 26/26] selftests/x86: Add tests for instruction str and sldt Ricardo Neri <ricardo.neri-calderon@linux.intel.com> - 2017-05-05 20:20 +0200
  [PATCH v7 25/26] selftests/x86: Add tests for User-Mode Instruction Prevention Ricardo Neri <ricardo.neri-calderon@linux.intel.com> - 2017-05-05 20:20 +0200
  [PATCH v7 13/26] x86/insn-eval: Add function to get default params of code segment Ricardo Neri <ricardo.neri-calderon@linux.intel.com> - 2017-05-05 20:20 +0200
  [PATCH v7 10/26] x86/insn-eval: Add utility functions to get segment selector Ricardo Neri <ricardo.neri-calderon@linux.intel.com> - 2017-05-05 20:20 +0200
  [PATCH v7 24/26] x86: Enable User-Mode Instruction Prevention Ricardo Neri <ricardo.neri-calderon@linux.intel.com> - 2017-05-05 20:20 +0200
  [PATCH v7 20/26] x86/cpufeature: Add User-Mode Instruction Prevention definitions Ricardo Neri <ricardo.neri-calderon@linux.intel.com> - 2017-05-05 20:20 +0200
    Re: [PATCH v7 20/26] x86/cpufeature: Add User-Mode Instruction  Prevention definitions Paolo Bonzini <pbonzini@redhat.com> - 2017-05-06 11:10 +0200
      Re: [PATCH v7 20/26] x86/cpufeature: Add User-Mode Instruction  Prevention definitions Ricardo Neri <ricardo.neri-calderon@linux.intel.com> - 2017-05-11 05:30 +0200
  [PATCH v7 12/26] x86/insn-eval: Add utility functions to get segment descriptor base address and limit Ricardo Neri <ricardo.neri-calderon@linux.intel.com> - 2017-05-05 20:20 +0200
  [PATCH v7 14/26] x86/insn-eval: Indicate a 32-bit displacement if ModRM.mod is 0 and ModRM.rm is 5 Ricardo Neri <ricardo.neri-calderon@linux.intel.com> - 2017-05-05 20:20 +0200
  [PATCH v7 16/26] x86/insn-eval: Support both signed 32-bit and 64-bit effective addresses Ricardo Neri <ricardo.neri-calderon@linux.intel.com> - 2017-05-05 20:20 +0200
  [PATCH v7 03/26] x86/mpx: Use signed variables to compute effective addresses Ricardo Neri <ricardo.neri-calderon@linux.intel.com> - 2017-05-05 20:20 +0200
  [PATCH v7 06/26] x86/mpx, x86/insn: Relocate insn util functions to a new insn-eval file Ricardo Neri <ricardo.neri-calderon@linux.intel.com> - 2017-05-05 20:30 +0200
  [PATCH v7 19/26] x86/insn-eval: Add wrapper function for 16-bit and 32-bit address encodings Ricardo Neri <ricardo.neri-calderon@linux.intel.com> - 2017-05-05 20:30 +0200
  [PATCH v7 15/26] x86/insn-eval: Incorporate segment base and limit in linear address computation Ricardo Neri <ricardo.neri-calderon@linux.intel.com> - 2017-05-05 20:30 +0200
  [PATCH v7 05/26] x86/mpx: Do not use SIB.base if its value is 101b and ModRM.mod = 0 Ricardo Neri <ricardo.neri-calderon@linux.intel.com> - 2017-05-05 20:30 +0200
  [PATCH v7 09/26] x86/insn-eval: Add utility function to identify string instructions Ricardo Neri <ricardo.neri-calderon@linux.intel.com> - 2017-05-05 20:30 +0200
  [PATCH v7 22/26] x86/umip: Force a page fault when unable to copy emulated result to user Ricardo Neri <ricardo.neri-calderon@linux.intel.com> - 2017-05-05 20:30 +0200
  [PATCH v7 04/26] x86/mpx: Do not use SIB.index if its value is 100b and ModRM.mod is not 11b Ricardo Neri <ricardo.neri-calderon@linux.intel.com> - 2017-05-05 20:30 +0200
  [PATCH v7 07/26] x86/insn-eval: Do not BUG on invalid register type Ricardo Neri <ricardo.neri-calderon@linux.intel.com> - 2017-05-05 20:30 +0200
  [PATCH v7 11/26] x86/insn-eval: Add utility function to get segment descriptor Ricardo Neri <ricardo.neri-calderon@linux.intel.com> - 2017-05-05 20:30 +0200
  [PATCH v7 17/26] x86/insn-eval: Handle 32-bit address encodings in virtual-8086 mode Ricardo Neri <ricardo.neri-calderon@linux.intel.com> - 2017-05-05 20:30 +0200
  [PATCH v7 08/26] x86/insn-eval: Add a utility function to get register offsets Ricardo Neri <ricardo.neri-calderon@linux.intel.com> - 2017-05-05 20:30 +0200
  [PATCH v7 02/26] x86/mm: Relocate page fault error codes to traps.h Ricardo Neri <ricardo.neri-calderon@linux.intel.com> - 2017-05-05 20:30 +0200
  [PATCH v7 18/26] x86/insn-eval: Add support to resolve 16-bit addressing encodings Ricardo Neri <ricardo.neri-calderon@linux.intel.com> - 2017-05-05 20:30 +0200
  [PATCH v7 21/26] x86: Add emulation code for UMIP instructions Ricardo Neri <ricardo.neri-calderon@linux.intel.com> - 2017-05-05 20:30 +0200

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