Re: [v3 PATCH 00/10] x86: Enable User-Mode Instruction Prevention

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From	Ricardo Neri <ricardo.neri-calderon@linux.intel.com>
Newsgroups	linux.kernel
Subject	Re: [v3 PATCH 00/10] x86: Enable User-Mode Instruction Prevention
Date	Thu, 26 Jan 2017 07:00:01 +0100
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Hi Peter,
On Wed, 2017-01-25 at 12:34 -0800, H. Peter Anvin wrote:
> On 01/25/17 12:23, Ricardo Neri wrote:
> >  * SMSW returns the value with which the CR0 register is programmed in
> >    head_32/64.S at boot time. This is, the following bits are enabed:
> >    CR0.0 for Protection Enable, CR.1 for Monitor Coprocessor, CR.4 for
> >    Extension Type, which will always be 1 in recent processors with UMIP;
> >    CR.5 for Numeric Error, CR0.16 for Write Protect, CR0.18 for Alignment
> >    Mask. Additionally, in x86_64, CR0.31 for Paging is set.
> 
> SMSW only returns CR0[15:0], so the reference here to CR0[31:16] seems odd.

I checked again the latest version (from Dec 2016) of the Intel Software
Development Manual. The documentation for SMSW states the following:

SMSW r16 operand size 16, store CR0[15:0] in r16
SMSW r32 operand size 32, zero-extend CR0[31:0], and store in r32
SMSW r64 operand size 64, zero-extend CR0[63:0], and store in r64

When the operand is a memory location, yes, it only returns CR0[15:0]

Also, in the tests that I ran I wrote the result of SMSW to a 64-bit
register. I get 0x80050033. It seems to me that it does write as many
bits as the register operand can hold.

Am I missing something?

Thanks and BR,
Ricardo
> 
> 	-hpa
> 
>

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[v3 PATCH 00/10] x86: Enable User-Mode Instruction Prevention Ricardo Neri <ricardo.neri-calderon@linux.intel.com> - 2017-01-25 21:30 +0100
  [v3 PATCH 07/10] x86: Add emulation code for UMIP instructions Ricardo Neri <ricardo.neri-calderon@linux.intel.com> - 2017-01-25 21:30 +0100
    Re: [v3 PATCH 07/10] x86: Add emulation code for UMIP instructions "H. Peter Anvin" <hpa@zytor.com> - 2017-01-25 21:50 +0100
      Re: [v3 PATCH 07/10] x86: Add emulation code for UMIP instructions Ricardo Neri <ricardo.neri-calderon@linux.intel.com> - 2017-01-26 07:00 +0100
  [v3 PATCH 01/10] x86/mpx: Do not use SIB index if index points to R/ESP Ricardo Neri <ricardo.neri-calderon@linux.intel.com> - 2017-01-25 21:30 +0100
  [v3 PATCH 09/10] x86: Enable User-Mode Instruction Prevention Ricardo Neri <ricardo.neri-calderon@linux.intel.com> - 2017-01-25 21:30 +0100
  [v3 PATCH 03/10] x86/mpx, x86/insn: Relocate insn util functions to a new insn-kernel Ricardo Neri <ricardo.neri-calderon@linux.intel.com> - 2017-01-25 21:30 +0100
    Re: [v3 PATCH 03/10] x86/mpx, x86/insn: Relocate insn util  functions to a new insn-kernel Masami Hiramatsu <mhiramat@kernel.org> - 2017-01-26 03:30 +0100
  [v3 PATCH 10/10] selftests/x86: Add tests for User-Mode Instruction Prevention Ricardo Neri <ricardo.neri-calderon@linux.intel.com> - 2017-01-25 21:30 +0100
  [v3 PATCH 05/10] x86/insn-kernel: Add support to resolve 16-bit addressing encodings Ricardo Neri <ricardo.neri-calderon@linux.intel.com> - 2017-01-25 21:30 +0100
    Re: [v3 PATCH 05/10] x86/insn-kernel: Add support to resolve 16-bit  addressing encodings Andy Lutomirski <luto@amacapital.net> - 2017-01-25 23:00 +0100
      Re: [v3 PATCH 05/10] x86/insn-kernel: Add support to resolve 16-bit addressing encodings "H. Peter Anvin" <hpa@zytor.com> - 2017-01-25 23:10 +0100
      Re: [v3 PATCH 05/10] x86/insn-kernel: Add support to resolve 16-bit  addressing encodings Ricardo Neri <ricardo.neri-calderon@linux.intel.com> - 2017-01-26 07:00 +0100
        Re: [v3 PATCH 05/10] x86/insn-kernel: Add support to resolve 16-bit  addressing encodings Andy Lutomirski <luto@amacapital.net> - 2017-01-26 18:20 +0100
          Re: [v3 PATCH 05/10] x86/insn-kernel: Add support to resolve 16-bit  addressing encodings Ricardo Neri <ricardo.neri-calderon@linux.intel.com> - 2017-01-27 04:50 +0100
  [v3 PATCH 02/10] x86/mpx: Fail decoding when SIB baseR/EBP is and no displacement is used Ricardo Neri <ricardo.neri-calderon@linux.intel.com> - 2017-01-25 21:30 +0100
  [v3 PATCH 08/10] x86/traps: Fixup general protection faults caused by UMIP Ricardo Neri <ricardo.neri-calderon@linux.intel.com> - 2017-01-25 21:30 +0100
  [v3 PATCH 04/10] x86/insn-kernel: Add a function to obtain register offset in ModRM Ricardo Neri <ricardo.neri-calderon@linux.intel.com> - 2017-01-25 21:30 +0100
    Re: [v3 PATCH 04/10] x86/insn-kernel: Add a function to obtain  register offset in ModRM Masami Hiramatsu <mhiramat@kernel.org> - 2017-01-26 03:20 +0100
      Re: [v3 PATCH 04/10] x86/insn-kernel: Add a function to obtain  register offset in ModRM Ricardo Neri <ricardo.neri-calderon@linux.intel.com> - 2017-01-26 07:10 +0100
        Re: [v3 PATCH 04/10] x86/insn-kernel: Add a function to obtain  register offset in ModRM Masami Hiramatsu <mhiramat@kernel.org> - 2017-01-27 09:00 +0100
  Re: [v3 PATCH 00/10] x86: Enable User-Mode Instruction Prevention "H. Peter Anvin" <hpa@zytor.com> - 2017-01-25 21:50 +0100
    Re: [v3 PATCH 00/10] x86: Enable User-Mode Instruction Prevention Ricardo Neri <ricardo.neri-calderon@linux.intel.com> - 2017-01-26 07:00 +0100

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