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Groups > linux.kernel > #1565249
| From | Thomas Gleixner <tglx@linutronix.de> |
|---|---|
| Newsgroups | linux.kernel |
| Subject | Re: [PATCH 1/8] Documentation, x86: Documentation for Intel Mem b/w allocation user interface |
| Date | 2017-01-23 20:10 +0100 |
| Message-ID | <t2Sa5-1ST-11@gated-at.bofh.it> (permalink) |
| References | (1 earlier) <sYaqZ-5m6-11@gated-at.bofh.it> <t0fPA-14g-7@gated-at.bofh.it> <t0MLv-5CY-1@gated-at.bofh.it> <t0Vc6-2mj-13@gated-at.bofh.it> <t2S0q-1AD-27@gated-at.bofh.it> |
| Organization | linux.* mail to news gateway |
On Mon, 23 Jan 2017, Shivappa Vikas wrote: > On Wed, 18 Jan 2017, Thomas Gleixner wrote: > > If it's going to stay, then Intel should be able to provide simple tables > > which give us the required information for a particular CPU model. > > By sample table - does this mean we can map a throttle value in non-linear > scale to its percentage ? Exactly. And that map should be provided by Intel simply because it's a royal pain in the neck if users have to map random power of 2 values to something useful. And of course every user has to do the same thing on their own. That'd be more than silly. Thanks, tglx
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Re: [PATCH 1/8] Documentation, x86: Documentation for Intel Mem b/w allocation user interface Shivappa Vikas <vikas.shivappa@intel.com> - 2017-01-18 02:00 +0100
Re: [PATCH 1/8] Documentation, x86: Documentation for Intel Mem b/w allocation user interface Thomas Gleixner <tglx@linutronix.de> - 2017-01-18 11:00 +0100
Re: [PATCH 1/8] Documentation, x86: Documentation for Intel Mem b/w allocation user interface Shivappa Vikas <vikas.shivappa@intel.com> - 2017-01-23 20:00 +0100
Re: [PATCH 1/8] Documentation, x86: Documentation for Intel Mem b/w allocation user interface Thomas Gleixner <tglx@linutronix.de> - 2017-01-23 20:10 +0100
Re: [PATCH 1/8] Documentation, x86: Documentation for Intel Mem b/w allocation user interface Shivappa Vikas <vikas.shivappa@intel.com> - 2017-01-24 23:20 +0100
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