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Re: [PATCH 2/4] ARM: nommu: dynamic exception base address setting

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Hi,

On Thu, Jan 19, 2017 at 01:59:09PM +0000, Vladimir Murzin wrote:
> On 18/01/17 20:38, afzal mohammed wrote:

> > +#define ID_PFR1_SE (0x3 << 4)	/* Security extension enable bits */
> 
> This bitfiled is 4 bits wide.

Since only 2 LSb's out of the 4 were enough to detect whether security
extensions were enabled, it was done so. i am going to use your below
suggestion & this would be taken care by that.

> > +	if (security_extensions_enabled()) {
> 
> You can use
> 
>     cpuid_feature_extract(CPUID_EXT_PFR1, 4)
>     
> and add a comment explaining what we are looking for and why.

Yes, that is better, was not aware of this, did saw CPUID_EXT_PFR1 as
an unused macro.

> > +#ifdef CONFIG_CPU_CP15
> > +	vectors_base = setup_vectors_base();
> > +#endif
> 
> alternatively it can be
> 
> 	unsigned long vector_base = IS_ENABLED(CONFIG_CPU_CP15) ? setup_vbar() : 0;

Yes that certainly is better.

Regards
afzal

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[PATCH 2/4] ARM: nommu: dynamic exception base address setting afzal mohammed <afzal.mohd.ma@gmail.com> - 2017-01-18 21:40 +0100
  Re: [PATCH 2/4] ARM: nommu: dynamic exception base address setting Vladimir Murzin <vladimir.murzin@arm.com> - 2017-01-19 15:00 +0100
    Re: [PATCH 2/4] ARM: nommu: dynamic exception base address setting Afzal Mohammed <afzal.mohd.ma@gmail.com> - 2017-01-20 17:30 +0100
      Re: [PATCH 2/4] ARM: nommu: dynamic exception base address setting Afzal Mohammed <afzal.mohd.ma@gmail.com> - 2017-01-22 04:40 +0100

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