[PATCH] clk: rockchip: fix the incorrect pclk_edp div width for RK3399

Path	csiph.com!1.us.feeder.erje.net!feeder.erje.net!2.eu.feeder.erje.net!news2.arglkargh.de!news.mixmin.net!aioe.org!news.servidellagleba.it!bofh.it!news.nic.it!robomod
From	Xing Zheng <zhengxing@rock-chips.com>
Newsgroups	linux.kernel
Subject	[PATCH] clk: rockchip: fix the incorrect pclk_edp div width for RK3399
Date	Wed, 18 Jan 2017 05:30:02 +0100
Message-ID	<t0Q2J-7Ky-3@gated-at.bofh.it> (permalink)
X-263anti-Spam	KSV:0;
X-Mail-Delivery	1
X-Abs-Checked	4
X-Rl-Sender	zhengxing@rock-chips.com
X-Fst-To	heiko@sntech.de
X-Sender-IP	103.29.142.67
X-Login-Name	zhengxing@rock-chips.com
X-Unique-Tag	<999aa3232456a921f25bdfbcd9153cb5>
X-Sender	zhengxing@rock-chips.com
X-Mailer	git-send-email 2.7.4
Sender	robomod@news.nic.it
List-ID	<linux-kernel.vger.kernel.org>
X-Mailing-List	linux-kernel@vger.kernel.org
Approved	robomod@news.nic.it
Lines	24
Organization	linux.* mail to news gateway
X-Original-Cc	dianders@google.com, linux-rockchip@lists.infradead.org, hl@rock-chips.com, Xing Zheng <zhengxing@rock-chips.com>, Michael Turquette <mturquette@baylibre.com>, Stephen Boyd <sboyd@codeaurora.org>, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org
X-Original-Date	Wed, 18 Jan 2017 12:20:56 +0800
X-Original-Message-ID	<1484713256-3005-1-git-send-email-zhengxing@rock-chips.com>
X-Original-Sender	linux-kernel-owner@vger.kernel.org
Xref	csiph.com linux.kernel:1561260

Show key headers only | View raw

The range of the  pclk_edp_div_con is [13:8] and 6 bits, not 5.

Reported-by: Lin Huang <hl@rock-chips.com>
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
---

 drivers/clk/rockchip/clk-rk3399.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/clk/rockchip/clk-rk3399.c b/drivers/clk/rockchip/clk-rk3399.c
index 3490887..73121b14 100644
--- a/drivers/clk/rockchip/clk-rk3399.c
+++ b/drivers/clk/rockchip/clk-rk3399.c
@@ -1132,7 +1132,7 @@ static struct rockchip_clk_branch rk3399_clk_branches[] __initdata = {
 			RK3399_CLKGATE_CON(11), 8, GFLAGS),
 
 	COMPOSITE(PCLK_EDP, "pclk_edp", mux_pll_src_cpll_gpll_p, 0,
-			RK3399_CLKSEL_CON(44), 15, 1, MFLAGS, 8, 5, DFLAGS,
+			RK3399_CLKSEL_CON(44), 15, 1, MFLAGS, 8, 6, DFLAGS,
 			RK3399_CLKGATE_CON(11), 11, GFLAGS),
 	GATE(PCLK_EDP_NOC, "pclk_edp_noc", "pclk_edp", CLK_IGNORE_UNUSED,
 			RK3399_CLKGATE_CON(32), 12, GFLAGS),
-- 
2.7.4

Back to linux.kernel | Previous | Next — Next in thread | Find similar | Unroll thread

Thread

[PATCH] clk: rockchip: fix the incorrect pclk_edp div width for RK3399 Xing Zheng <zhengxing@rock-chips.com> - 2017-01-18 05:30 +0100
  Re: [PATCH] clk: rockchip: fix the incorrect pclk_edp div width for RK3399 Heiko Stübner <heiko@sntech.de> - 2017-01-18 12:30 +0100

csiph-web