Groups | Search | Server Info | Keyboard shortcuts | Login | Register [http] [https] [nntp] [nntps]
Groups > linux.kernel > #1512260
| From | Thomas Gleixner <tglx@linutronix.de> |
|---|---|
| Newsgroups | linux.kernel |
| Subject | Re: [PATCH v7 3/4] x86/cpufeature: Add PHIR3MWAIT to CPU features |
| Date | 2016-10-31 02:20 +0100 |
| Message-ID | <sy9qx-3UZ-23@gated-at.bofh.it> (permalink) |
| References | <sxfRn-Aj-3@gated-at.bofh.it> <sxfRn-Aj-1@gated-at.bofh.it> |
| Organization | linux.* mail to news gateway |
On Fri, 28 Oct 2016, Grzegorz Andrejczuk wrote: > Add Intel Xeon Phi x200 (KnightsLanding) cpu feature - ring 3 monitor/mwait > > Signed-off-by: Grzegorz Andrejczuk <grzegorz.andrejczuk@intel.com> > --- > arch/x86/include/asm/cpufeatures.h | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h > index 92a8308..eb88eeb 100644 > --- a/arch/x86/include/asm/cpufeatures.h > +++ b/arch/x86/include/asm/cpufeatures.h > @@ -101,6 +101,7 @@ > #define X86_FEATURE_TSC_RELIABLE ( 3*32+23) /* TSC is known to be reliable */ > #define X86_FEATURE_NONSTOP_TSC ( 3*32+24) /* TSC does not stop in C states */ > /* free, was #define X86_FEATURE_CLFLUSH_MONITOR ( 3*32+25) * "" clflush reqd with monitor */ Bah. Do you really think that this comment is still useful? Can you please get your act together and switch on your brain instead of mindlessly slapping stuff into the code? > +#define X86_FEATURE_PHIR3MWAIT ( 3*32+25) /* Xeon Phi x200 ring 3 MONITOR/MWAIT */ Thanks, tglx
Back to linux.kernel | Previous | Next — Previous in thread | Find similar | Unroll thread
[PATCH v7 3/4] x86/cpufeature: Add PHIR3MWAIT to CPU features Grzegorz Andrejczuk <grzegorz.andrejczuk@intel.com> - 2016-10-28 16:00 +0200 Re: [PATCH v7 3/4] x86/cpufeature: Add PHIR3MWAIT to CPU features Thomas Gleixner <tglx@linutronix.de> - 2016-10-31 02:20 +0100
csiph-web