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Groups > linux.kernel > #1511141
| From | Grzegorz Andrejczuk <grzegorz.andrejczuk@intel.com> |
|---|---|
| Newsgroups | linux.kernel |
| Subject | [PATCH v7 3/4] x86/cpufeature: Add PHIR3MWAIT to CPU features |
| Date | 2016-10-28 16:00 +0200 |
| Message-ID | <sxfRn-Aj-1@gated-at.bofh.it> (permalink) |
| References | <sxfRn-Aj-3@gated-at.bofh.it> |
| Organization | linux.* mail to news gateway |
Add Intel Xeon Phi x200 (KnightsLanding) cpu feature - ring 3 monitor/mwait Signed-off-by: Grzegorz Andrejczuk <grzegorz.andrejczuk@intel.com> --- arch/x86/include/asm/cpufeatures.h | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h index 92a8308..eb88eeb 100644 --- a/arch/x86/include/asm/cpufeatures.h +++ b/arch/x86/include/asm/cpufeatures.h @@ -101,6 +101,7 @@ #define X86_FEATURE_TSC_RELIABLE ( 3*32+23) /* TSC is known to be reliable */ #define X86_FEATURE_NONSTOP_TSC ( 3*32+24) /* TSC does not stop in C states */ /* free, was #define X86_FEATURE_CLFLUSH_MONITOR ( 3*32+25) * "" clflush reqd with monitor */ +#define X86_FEATURE_PHIR3MWAIT ( 3*32+25) /* Xeon Phi x200 ring 3 MONITOR/MWAIT */ #define X86_FEATURE_EXTD_APICID ( 3*32+26) /* has extended APICID (8 bits) */ #define X86_FEATURE_AMD_DCM ( 3*32+27) /* multi-node processor */ #define X86_FEATURE_APERFMPERF ( 3*32+28) /* APERFMPERF */ -- 2.5.1
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[PATCH v7 3/4] x86/cpufeature: Add PHIR3MWAIT to CPU features Grzegorz Andrejczuk <grzegorz.andrejczuk@intel.com> - 2016-10-28 16:00 +0200 Re: [PATCH v7 3/4] x86/cpufeature: Add PHIR3MWAIT to CPU features Thomas Gleixner <tglx@linutronix.de> - 2016-10-31 02:20 +0100
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