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Groups > linux.kernel > #1505475
| From | Peter Zijlstra <peterz@infradead.org> |
|---|---|
| Newsgroups | linux.kernel |
| Subject | Re: [PATCH v3] x86/tsc: add X86_FEATURE_TSC_KNOWN_FREQ flag |
| Date | 2016-10-21 07:50 +0200 |
| Message-ID | <suASm-1k5-3@gated-at.bofh.it> (permalink) |
| References | (5 earlier) <srmCe-1kH-7@gated-at.bofh.it> <srXs5-1E4-1@gated-at.bofh.it> <suisq-68t-15@gated-at.bofh.it> <suiC5-6ej-1@gated-at.bofh.it> <survH-3sZ-11@gated-at.bofh.it> |
| Organization | linux.* mail to news gateway |
On Thu, Oct 20, 2016 at 09:37:50PM +0200, Thomas Gleixner wrote: > Well, we have the same issue on other platforms/models which set the > reliable flag. I was not aware we had other platforms doing this, git grep tells me intel-mid does this as well.. > So one sanity check we can do is to read the IA32_TSC_ADJUST MSR on all > cores. They should all have the same value (usually 0) or at least have a > very minimal delta. If that's off by more than 1us then something is fishy > especially on single socket systems. We could at least WARN about it. > > We could do this in idle occasionally as well, so we can detect the dreaded > "SMI wants to hide the cycles" crapola. Indeed, that sounds like the best we can; and probably should; do.
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[PATCH v3] x86/tsc: add X86_FEATURE_TSC_KNOWN_FREQ flag Bin Gao <bin.gao@linux.intel.com> - 2016-10-14 01:20 +0200
Re: [PATCH v3] x86/tsc: add X86_FEATURE_TSC_KNOWN_FREQ flag Thomas Gleixner <tglx@linutronix.de> - 2016-10-20 12:10 +0200
Re: [PATCH v3] x86/tsc: add X86_FEATURE_TSC_KNOWN_FREQ flag Peter Zijlstra <peterz@infradead.org> - 2016-10-20 12:20 +0200
Re: [PATCH v3] x86/tsc: add X86_FEATURE_TSC_KNOWN_FREQ flag Thomas Gleixner <tglx@linutronix.de> - 2016-10-20 21:50 +0200
Re: [PATCH v3] x86/tsc: add X86_FEATURE_TSC_KNOWN_FREQ flag Peter Zijlstra <peterz@infradead.org> - 2016-10-21 07:50 +0200
Re: [PATCH v3] x86/tsc: add X86_FEATURE_TSC_KNOWN_FREQ flag Thomas Gleixner <tglx@linutronix.de> - 2016-10-21 10:10 +0200
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