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[PATCH 6/9] ARM: dts: sun6i: Sort pinmux setting nodes

From Chen-Yu Tsai <wens@csie.org>
Newsgroups linux.kernel
Subject [PATCH 6/9] ARM: dts: sun6i: Sort pinmux setting nodes
Date 2016-10-06 18:10 +0200
Message-ID <spjp8-2A0-19@gated-at.bofh.it> (permalink)
References <spjp7-2A0-5@gated-at.bofh.it>
Organization linux.* mail to news gateway

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The pinmux setting nodes for the A31 were added out of alphabetical
order. Sort them.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
---
 arch/arm/boot/dts/sun6i-a31.dtsi | 82 ++++++++++++++++++++--------------------
 1 file changed, 41 insertions(+), 41 deletions(-)

diff --git a/arch/arm/boot/dts/sun6i-a31.dtsi b/arch/arm/boot/dts/sun6i-a31.dtsi
index ce1960453a0b..c1b891e75f18 100644
--- a/arch/arm/boot/dts/sun6i-a31.dtsi
+++ b/arch/arm/boot/dts/sun6i-a31.dtsi
@@ -434,13 +434,48 @@
 			#interrupt-cells = <3>;
 			#gpio-cells = <3>;
 
-			uart0_pins_a: uart0@0 {
-				allwinner,pins = "PH20", "PH21";
-				allwinner,function = "uart0";
+			gmac_pins_gmii_a: gmac_gmii@0 {
+				allwinner,pins = "PA0", "PA1", "PA2", "PA3",
+						"PA4", "PA5", "PA6", "PA7",
+						"PA8", "PA9", "PA10", "PA11",
+						"PA12", "PA13", "PA14",	"PA15",
+						"PA16", "PA17", "PA18", "PA19",
+						"PA20", "PA21", "PA22", "PA23",
+						"PA24", "PA25", "PA26", "PA27";
+				allwinner,function = "gmac";
+				/*
+				 * data lines in GMII mode run at 125MHz and
+				 * might need a higher signal drive strength
+				 */
+				allwinner,drive = <SUN4I_PINCTRL_30_MA>;
+				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+			};
+
+			gmac_pins_mii_a: gmac_mii@0 {
+				allwinner,pins = "PA0", "PA1", "PA2", "PA3",
+						"PA8", "PA9", "PA11",
+						"PA12", "PA13", "PA14", "PA19",
+						"PA20", "PA21", "PA22", "PA23",
+						"PA24", "PA26", "PA27";
+				allwinner,function = "gmac";
 				allwinner,drive = <SUN4I_PINCTRL_10_MA>;
 				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 			};
 
+			gmac_pins_rgmii_a: gmac_rgmii@0 {
+				allwinner,pins = "PA0", "PA1", "PA2", "PA3",
+						"PA9", "PA10", "PA11",
+						"PA12", "PA13", "PA14", "PA19",
+						"PA20", "PA25", "PA26", "PA27";
+				allwinner,function = "gmac";
+				/*
+				 * data lines in RGMII mode use DDR mode
+				 * and need a higher signal drive strength
+				 */
+				allwinner,drive = <SUN4I_PINCTRL_40_MA>;
+				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+			};
+
 			i2c0_pins_a: i2c0@0 {
 				allwinner,pins = "PH14", "PH15";
 				allwinner,function = "i2c0";
@@ -506,47 +541,12 @@
 				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 			};
 
-			gmac_pins_mii_a: gmac_mii@0 {
-				allwinner,pins = "PA0", "PA1", "PA2", "PA3",
-						"PA8", "PA9", "PA11",
-						"PA12", "PA13", "PA14", "PA19",
-						"PA20", "PA21", "PA22", "PA23",
-						"PA24", "PA26", "PA27";
-				allwinner,function = "gmac";
+			uart0_pins_a: uart0@0 {
+				allwinner,pins = "PH20", "PH21";
+				allwinner,function = "uart0";
 				allwinner,drive = <SUN4I_PINCTRL_10_MA>;
 				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 			};
-
-			gmac_pins_gmii_a: gmac_gmii@0 {
-				allwinner,pins = "PA0", "PA1", "PA2", "PA3",
-						"PA4", "PA5", "PA6", "PA7",
-						"PA8", "PA9", "PA10", "PA11",
-						"PA12", "PA13", "PA14",	"PA15",
-						"PA16", "PA17", "PA18", "PA19",
-						"PA20", "PA21", "PA22", "PA23",
-						"PA24", "PA25", "PA26", "PA27";
-				allwinner,function = "gmac";
-				/*
-				 * data lines in GMII mode run at 125MHz and
-				 * might need a higher signal drive strength
-				 */
-				allwinner,drive = <SUN4I_PINCTRL_30_MA>;
-				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
-			};
-
-			gmac_pins_rgmii_a: gmac_rgmii@0 {
-				allwinner,pins = "PA0", "PA1", "PA2", "PA3",
-						"PA9", "PA10", "PA11",
-						"PA12", "PA13", "PA14", "PA19",
-						"PA20", "PA25", "PA26", "PA27";
-				allwinner,function = "gmac";
-				/*
-				 * data lines in RGMII mode use DDR mode
-				 * and need a higher signal drive strength
-				 */
-				allwinner,drive = <SUN4I_PINCTRL_40_MA>;
-				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
-			};
 		};
 
 		timer@01c20c00 {
-- 
2.9.3

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Thread

[PATCH 0/9] drm/sun4i: Support first display pipeline on sun6i Chen-Yu Tsai <wens@csie.org> - 2016-10-06 18:10 +0200
  [PATCH 5/9] drm/sun4i: Add compatible strings for A31/A31s display pipelines Chen-Yu Tsai <wens@csie.org> - 2016-10-06 18:10 +0200
    Re: [PATCH 5/9] drm/sun4i: Add compatible strings for A31/A31s  display pipelines Rob Herring <robh@kernel.org> - 2016-10-10 16:50 +0200
  [PATCH 7/9] ARM: dts: sun6i: Add device nodes for first display pipeline Chen-Yu Tsai <wens@csie.org> - 2016-10-06 18:10 +0200
  [PATCH 6/9] ARM: dts: sun6i: Sort pinmux setting nodes Chen-Yu Tsai <wens@csie.org> - 2016-10-06 18:10 +0200
    Re: [PATCH 6/9] ARM: dts: sun6i: Sort pinmux setting nodes Maxime Ripard <maxime.ripard@free-electrons.com> - 2016-10-07 15:10 +0200
  [PATCH 4/9] drm/sun4i: Add compatible string for A31/A31s TCON (timing controller) Chen-Yu Tsai <wens@csie.org> - 2016-10-06 18:10 +0200
    Re: [PATCH 4/9] drm/sun4i: Add compatible string for A31/A31s TCON  (timing controller) Maxime Ripard <maxime.ripard@free-electrons.com> - 2016-10-07 15:10 +0200
  [PATCH 8/9] ARM: dts: sun6i: Add A31 LCD0 RGB888 pins Chen-Yu Tsai <wens@csie.org> - 2016-10-06 18:10 +0200
  [PATCH 3/9] drm/sun4i: Put dotclock range into tcon quirks and check against them Chen-Yu Tsai <wens@csie.org> - 2016-10-06 18:10 +0200
    Re: [PATCH 3/9] drm/sun4i: Put dotclock range into tcon quirks and  check against them Maxime Ripard <maxime.ripard@free-electrons.com> - 2016-10-07 15:10 +0200
  [PATCH 9/9] [DO NOT MERGE] ARM: dts: sun6i: Enable 7" LCD panel on Sinlinx SinA31s Chen-Yu Tsai <wens@csie.org> - 2016-10-06 18:10 +0200
  [PATCH 2/9] drm/sun4i: tcon: Move SoC specific quirks to a DT matched data structure Chen-Yu Tsai <wens@csie.org> - 2016-10-06 18:10 +0200
    Re: [PATCH 2/9] drm/sun4i: tcon: Move SoC specific quirks to a DT  matched data structure Maxime Ripard <maxime.ripard@free-electrons.com> - 2016-10-07 15:10 +0200
      Re: [PATCH 2/9] drm/sun4i: tcon: Move SoC specific quirks to a DT  matched data structure Chen-Yu Tsai <wens@csie.org> - 2016-10-11 11:20 +0200
        Re: [PATCH 2/9] drm/sun4i: tcon: Move SoC specific quirks to a DT  matched data structure Maxime Ripard <maxime.ripard@free-electrons.com> - 2016-10-11 11:40 +0200

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