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Groups > linux.kernel > #1497609
| From | "Fenghua Yu" <fenghua.yu@intel.com> |
|---|---|
| Newsgroups | linux.kernel |
| Subject | [PATCH v3 10/18] x86/intel_rdt: Build structures for each resource based on cache topology |
| Date | 2016-10-08 01:50 +0200 |
| Message-ID | <spN3R-7BE-37@gated-at.bofh.it> (permalink) |
| References | <spN3Q-7BE-3@gated-at.bofh.it> |
| Organization | linux.* mail to news gateway |
From: Tony Luck <tony.luck@intel.com>
We use the cpu hotplug notifier to catch each cpu in turn and look at
its cache topology w.r.t each of the resource groups. As we discover
new resources, we initialize the bitmask array for each to the default
(full access) value.
Signed-off-by: Tony Luck <tony.luck@intel.com>
Signed-off-by: Fenghua Yu <fenghua.yu@intel.com>
---
arch/x86/include/asm/intel_rdt.h | 35 ++++++++++
arch/x86/kernel/cpu/intel_rdt.c | 135 +++++++++++++++++++++++++++++++++++++++
2 files changed, 170 insertions(+)
diff --git a/arch/x86/include/asm/intel_rdt.h b/arch/x86/include/asm/intel_rdt.h
index 251ac2a..bad8dc7 100644
--- a/arch/x86/include/asm/intel_rdt.h
+++ b/arch/x86/include/asm/intel_rdt.h
@@ -40,6 +40,39 @@ struct rdt_resource {
if (r->enabled)
#define IA32_L3_CBM_BASE 0xc90
+
+/**
+ * struct rdt_domain - group of cpus sharing an RDT resource
+ * @list: all instances of this resource
+ * @id: unique id for this instance
+ * @cpu_mask: which cpus share this resource
+ * @cbm: array of cache bit masks (indexed by CLOSID)
+ */
+struct rdt_domain {
+ struct list_head list;
+ int id;
+ struct cpumask cpu_mask;
+ u32 *cbm;
+};
+
+/**
+ * struct msr_param - set a range of MSRs from a domain
+ * @res: The resource to use
+ * @low: Beginning index from base MSR
+ * @high: End index
+ */
+struct msr_param {
+ struct rdt_resource *res;
+ int low;
+ int high;
+};
+
+extern struct static_key_false rdt_enable_key;
+extern struct mutex rdtgroup_mutex;
+
+int __init rdtgroup_init(void);
+
+extern struct rdtgroup *rdtgroup_default;
extern struct rdt_resource rdt_resources_all[];
enum {
@@ -64,4 +97,6 @@ union cpuid_0x10_1_edx {
} split;
unsigned int full;
};
+
+void rdt_cbm_update(void *arg);
#endif /* _ASM_X86_INTEL_RDT_H */
diff --git a/arch/x86/kernel/cpu/intel_rdt.c b/arch/x86/kernel/cpu/intel_rdt.c
index b9b1e9e..76b7476 100644
--- a/arch/x86/kernel/cpu/intel_rdt.c
+++ b/arch/x86/kernel/cpu/intel_rdt.c
@@ -24,12 +24,18 @@
#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
+#include <linux/cacheinfo.h>
#include <linux/slab.h>
#include <linux/err.h>
+#include <linux/cpuhotplug.h>
+
#include <asm/intel_rdt_common.h>
#include <asm/intel-family.h>
#include <asm/intel_rdt.h>
+/* Mutex to protect rdtgroup access. */
+DEFINE_MUTEX(rdtgroup_mutex);
+
int rdt_max_closid;
#define domain_init(name) LIST_HEAD_INIT(rdt_resources_all[name].domains)
@@ -119,14 +125,143 @@ static inline bool get_rdt_resources(struct cpuinfo_x86 *c)
return ret;
}
+static int get_cache_id(int cpu, int level)
+{
+ struct cpu_cacheinfo *ci = get_cpu_cacheinfo(cpu);
+ int i;
+
+ for (i = 0; i < ci->num_leaves; i++)
+ if (ci->info_list[i].level == level)
+ return ci->info_list[i].id;
+ return -1;
+}
+
+void rdt_cbm_update(void *arg)
+{
+ struct msr_param *m = (struct msr_param *)arg;
+ struct rdt_resource *r = m->res;
+ struct rdt_domain *d;
+ struct list_head *l;
+ int i, cpu = smp_processor_id();
+
+ list_for_each(l, &r->domains) {
+ d = list_entry(l, struct rdt_domain, list);
+ if (cpumask_test_cpu(cpu, &d->cpu_mask))
+ goto found;
+ }
+ pr_info_once("cpu %d not found in any domain for resource %s\n",
+ cpu, r->name);
+
+found:
+ for (i = m->low; i < m->high; i++)
+ wrmsrl(r->msr_base + i, d->cbm[i]);
+}
+
+static void update_domain(int cpu, struct rdt_resource *r, int add)
+{
+ struct list_head *l;
+ struct rdt_domain *d;
+ int i, cache_id;
+
+ cache_id = get_cache_id(cpu, r->cache_level);
+
+ if (cache_id == -1) {
+ pr_info_once("Could't find cache id for cpu %d\n", cpu);
+ return;
+ }
+ list_for_each(l, &r->domains) {
+ d = list_entry(l, struct rdt_domain, list);
+ if (cache_id == d->id)
+ goto found;
+ if (cache_id < d->id)
+ break;
+ }
+ if (!add) {
+ pr_info_once("removed unknown cpu %d\n", cpu);
+ return;
+ }
+ d = kzalloc(sizeof(*d), GFP_KERNEL);
+ if (!d)
+ return;
+
+ d->id = cache_id;
+ d->cbm = kmalloc_array(r->max_closid, sizeof(*d->cbm), GFP_KERNEL);
+ if (!d->cbm) {
+ pr_info("Failed to alloc CBM array for cpu %d\n", cpu);
+ kfree(d);
+ return;
+ }
+ cpumask_set_cpu(cpu, &d->cpu_mask);
+ for (i = 0; i < r->max_closid; i++) {
+ d->cbm[i] = r->max_cbm;
+ wrmsrl(r->msr_base + i, d->cbm[i]);
+ }
+ list_add_tail(&d->list, l);
+ r->num_domains++;
+ return;
+
+found:
+ if (add) {
+ cpumask_set_cpu(cpu, &d->cpu_mask);
+ } else {
+ cpumask_clear_cpu(cpu, &d->cpu_mask);
+ if (cpumask_empty(&d->cpu_mask)) {
+ r->num_domains--;
+ kfree(d->cbm);
+ list_del(&d->list);
+ kfree(d);
+ }
+ }
+}
+
+static void rdt_reset_pqr_assoc_closid(void *v)
+{
+ struct intel_pqr_state *state = this_cpu_ptr(&pqr_state);
+
+ state->closid = 0;
+ wrmsr(MSR_IA32_PQR_ASSOC, state->rmid, 0);
+}
+
+static int intel_rdt_online_cpu(unsigned int cpu)
+{
+ struct rdt_resource *r;
+
+ mutex_lock(&rdtgroup_mutex);
+ for_each_rdt_resource(r)
+ update_domain(cpu, r, 1);
+ smp_call_function_single(cpu, rdt_reset_pqr_assoc_closid, NULL, 1);
+ mutex_unlock(&rdtgroup_mutex);
+
+ return 0;
+}
+
+static int intel_rdt_offline_cpu(unsigned int cpu)
+{
+ struct rdt_resource *r;
+
+ mutex_lock(&rdtgroup_mutex);
+ for_each_rdt_resource(r)
+ update_domain(cpu, r, 0);
+ mutex_unlock(&rdtgroup_mutex);
+
+ return 0;
+}
+
static int __init intel_rdt_late_init(void)
{
struct cpuinfo_x86 *c = &boot_cpu_data;
struct rdt_resource *r;
+ int ret;
if (!get_rdt_resources(c))
return -ENODEV;
+ ret = cpuhp_setup_state(CPUHP_AP_ONLINE_DYN,
+ "AP_INTEL_RDT_ONLINE",
+ intel_rdt_online_cpu, intel_rdt_offline_cpu);
+ if (ret < 0)
+ return ret;
+
for_each_rdt_resource(r)
rdt_max_closid = max(rdt_max_closid, r->max_closid);
--
2.5.0
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[PATCH v3 00/18] Intel Cache Allocation Technology "Fenghua Yu" <fenghua.yu@intel.com> - 2016-10-08 01:50 +0200
[PATCH v3 04/18] x86/intel_rdt: Feature discovery "Fenghua Yu" <fenghua.yu@intel.com> - 2016-10-08 01:50 +0200
Re: [PATCH v3 04/18] x86/intel_rdt: Feature discovery Nilay Vaish <nilayvaish@gmail.com> - 2016-10-08 19:20 +0200
Re: [PATCH v3 04/18] x86/intel_rdt: Feature discovery Fenghua Yu <fenghua.yu@intel.com> - 2016-10-08 20:00 +0200
Re: [PATCH v3 04/18] x86/intel_rdt: Feature discovery Borislav Petkov <bp@suse.de> - 2016-10-08 22:00 +0200
Re: [PATCH v3 04/18] x86/intel_rdt: Feature discovery Nilay Vaish <nilayvaish@gmail.com> - 2016-10-11 19:10 +0200
Re: [PATCH v3 04/18] x86/intel_rdt: Feature discovery Borislav Petkov <bp@suse.de> - 2016-10-11 19:10 +0200
Re: [PATCH v3 04/18] x86/intel_rdt: Feature discovery Dave Hansen <dave.hansen@intel.com> - 2016-10-10 18:10 +0200
Re: [PATCH v3 04/18] x86/intel_rdt: Feature discovery Borislav Petkov <bp@suse.de> - 2016-10-10 18:20 +0200
[PATCH v3 10/18] x86/intel_rdt: Build structures for each resource based on cache topology "Fenghua Yu" <fenghua.yu@intel.com> - 2016-10-08 01:50 +0200
Re: [PATCH v3 10/18] x86/intel_rdt: Build structures for each resource based on cache topology Nilay Vaish <nilayvaish@gmail.com> - 2016-10-10 00:00 +0200
[PATCH v3 16/18] x86/intel_rdt: Add schemata file "Fenghua Yu" <fenghua.yu@intel.com> - 2016-10-08 01:50 +0200
[PATCH v3 07/18] x86/intel_rdt: Add Haswell feature discovery "Fenghua Yu" <fenghua.yu@intel.com> - 2016-10-08 01:50 +0200
Re: [PATCH v3 07/18] x86/intel_rdt: Add Haswell feature discovery Borislav Petkov <bp@suse.de> - 2016-10-09 13:50 +0200
Re: [PATCH v3 07/18] x86/intel_rdt: Add Haswell feature discovery Fenghua Yu <fenghua.yu@intel.com> - 2016-10-09 16:10 +0200
Re: [PATCH v3 07/18] x86/intel_rdt: Add Haswell feature discovery Borislav Petkov <bp@suse.de> - 2016-10-09 18:30 +0200
Re: [PATCH v3 07/18] x86/intel_rdt: Add Haswell feature discovery "Luck, Tony" <tony.luck@intel.com> - 2016-10-10 21:00 +0200
Re: [PATCH v3 07/18] x86/intel_rdt: Add Haswell feature discovery Borislav Petkov <bp@suse.de> - 2016-10-11 13:20 +0200
RE: [PATCH v3 07/18] x86/intel_rdt: Add Haswell feature discovery "Luck, Tony" <tony.luck@intel.com> - 2016-10-11 17:00 +0200
[PATCH v3 13/18] x86/intel_rdt: Add mkdir to resctrl file system "Fenghua Yu" <fenghua.yu@intel.com> - 2016-10-08 01:50 +0200
Re: [PATCH v3 13/18] x86/intel_rdt: Add mkdir to resctrl file system Nilay Vaish <nilayvaish@gmail.com> - 2016-10-10 20:00 +0200
[RFC PATCH 19/18] x86/intel_rdt: Add support for L2 cache allocation "Luck, Tony" <tony.luck@intel.com> - 2016-10-08 02:00 +0200
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