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Groups > linux.kernel > #1497608
| From | "Fenghua Yu" <fenghua.yu@intel.com> |
|---|---|
| Newsgroups | linux.kernel |
| Subject | [PATCH v3 04/18] x86/intel_rdt: Feature discovery |
| Date | 2016-10-08 01:50 +0200 |
| Message-ID | <spN3R-7BE-35@gated-at.bofh.it> (permalink) |
| References | <spN3Q-7BE-3@gated-at.bofh.it> |
| Organization | linux.* mail to news gateway |
From: Fenghua Yu <fenghua.yu@intel.com>
Check CPUID leaves for all the Resource Director Technology (RDT)
Cache Allocation Technology (CAT) bits.
Prescence of allocation features:
CPUID.(EAX=7H, ECX=0):EBX[bit 15] X86_FEATURE_RDT_A
L2 and L3 caches are each separately enabled:
CPUID.(EAX=10H, ECX=0):EBX[bit 1] X86_FEATURE_CAT_L3
CPUID.(EAX=10H, ECX=0):EBX[bit 2] X86_FEATURE_CAT_L2
L3 cache may support independent control of allocation for
code and data (CDP = Code/Data Prioritization):
CPUID.(EAX=10H, ECX=1):ECX[bit 2] X86_FEATURE_CDP_L3
Signed-off-by: Fenghua Yu <fenghua.yu@intel.com>
Signed-off-by: Tony Luck <tony.luck@intel.com>
---
arch/x86/include/asm/cpufeatures.h | 5 +++++
arch/x86/kernel/cpu/scattered.c | 3 +++
2 files changed, 8 insertions(+)
diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h
index 92a8308..64dd8274 100644
--- a/arch/x86/include/asm/cpufeatures.h
+++ b/arch/x86/include/asm/cpufeatures.h
@@ -196,6 +196,10 @@
#define X86_FEATURE_INTEL_PT ( 7*32+15) /* Intel Processor Trace */
+#define X86_FEATURE_CAT_L3 ( 7*32+16) /* Cache Allocation Technology L3 */
+#define X86_FEATURE_CAT_L2 ( 7*32+17) /* Cache Allocation Technology L2 */
+#define X86_FEATURE_CDP_L3 ( 7*32+18) /* Code and Data Prioritization L3 */
+
/* Virtualization flags: Linux defined, word 8 */
#define X86_FEATURE_TPR_SHADOW ( 8*32+ 0) /* Intel TPR Shadow */
#define X86_FEATURE_VNMI ( 8*32+ 1) /* Intel Virtual NMI */
@@ -220,6 +224,7 @@
#define X86_FEATURE_RTM ( 9*32+11) /* Restricted Transactional Memory */
#define X86_FEATURE_CQM ( 9*32+12) /* Cache QoS Monitoring */
#define X86_FEATURE_MPX ( 9*32+14) /* Memory Protection Extension */
+#define X86_FEATURE_RDT_A ( 9*32+15) /* Resource Director Technology Allocation */
#define X86_FEATURE_AVX512F ( 9*32+16) /* AVX-512 Foundation */
#define X86_FEATURE_AVX512DQ ( 9*32+17) /* AVX-512 DQ (Double/Quad granular) Instructions */
#define X86_FEATURE_RDSEED ( 9*32+18) /* The RDSEED instruction */
diff --git a/arch/x86/kernel/cpu/scattered.c b/arch/x86/kernel/cpu/scattered.c
index 8cb57df..11f39a2 100644
--- a/arch/x86/kernel/cpu/scattered.c
+++ b/arch/x86/kernel/cpu/scattered.c
@@ -34,6 +34,9 @@ void init_scattered_cpuid_features(struct cpuinfo_x86 *c)
{ X86_FEATURE_INTEL_PT, CR_EBX,25, 0x00000007, 0 },
{ X86_FEATURE_APERFMPERF, CR_ECX, 0, 0x00000006, 0 },
{ X86_FEATURE_EPB, CR_ECX, 3, 0x00000006, 0 },
+ { X86_FEATURE_CAT_L3, CR_EBX, 1, 0x00000010, 0 },
+ { X86_FEATURE_CAT_L2, CR_EBX, 2, 0x00000010, 0 },
+ { X86_FEATURE_CDP_L3, CR_ECX, 2, 0x00000010, 1 },
{ X86_FEATURE_HW_PSTATE, CR_EDX, 7, 0x80000007, 0 },
{ X86_FEATURE_CPB, CR_EDX, 9, 0x80000007, 0 },
{ X86_FEATURE_PROC_FEEDBACK, CR_EDX,11, 0x80000007, 0 },
--
2.5.0
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[PATCH v3 00/18] Intel Cache Allocation Technology "Fenghua Yu" <fenghua.yu@intel.com> - 2016-10-08 01:50 +0200
[PATCH v3 04/18] x86/intel_rdt: Feature discovery "Fenghua Yu" <fenghua.yu@intel.com> - 2016-10-08 01:50 +0200
Re: [PATCH v3 04/18] x86/intel_rdt: Feature discovery Nilay Vaish <nilayvaish@gmail.com> - 2016-10-08 19:20 +0200
Re: [PATCH v3 04/18] x86/intel_rdt: Feature discovery Fenghua Yu <fenghua.yu@intel.com> - 2016-10-08 20:00 +0200
Re: [PATCH v3 04/18] x86/intel_rdt: Feature discovery Borislav Petkov <bp@suse.de> - 2016-10-08 22:00 +0200
Re: [PATCH v3 04/18] x86/intel_rdt: Feature discovery Nilay Vaish <nilayvaish@gmail.com> - 2016-10-11 19:10 +0200
Re: [PATCH v3 04/18] x86/intel_rdt: Feature discovery Borislav Petkov <bp@suse.de> - 2016-10-11 19:10 +0200
Re: [PATCH v3 04/18] x86/intel_rdt: Feature discovery Dave Hansen <dave.hansen@intel.com> - 2016-10-10 18:10 +0200
Re: [PATCH v3 04/18] x86/intel_rdt: Feature discovery Borislav Petkov <bp@suse.de> - 2016-10-10 18:20 +0200
[PATCH v3 10/18] x86/intel_rdt: Build structures for each resource based on cache topology "Fenghua Yu" <fenghua.yu@intel.com> - 2016-10-08 01:50 +0200
Re: [PATCH v3 10/18] x86/intel_rdt: Build structures for each resource based on cache topology Nilay Vaish <nilayvaish@gmail.com> - 2016-10-10 00:00 +0200
[PATCH v3 16/18] x86/intel_rdt: Add schemata file "Fenghua Yu" <fenghua.yu@intel.com> - 2016-10-08 01:50 +0200
[PATCH v3 07/18] x86/intel_rdt: Add Haswell feature discovery "Fenghua Yu" <fenghua.yu@intel.com> - 2016-10-08 01:50 +0200
Re: [PATCH v3 07/18] x86/intel_rdt: Add Haswell feature discovery Borislav Petkov <bp@suse.de> - 2016-10-09 13:50 +0200
Re: [PATCH v3 07/18] x86/intel_rdt: Add Haswell feature discovery Fenghua Yu <fenghua.yu@intel.com> - 2016-10-09 16:10 +0200
Re: [PATCH v3 07/18] x86/intel_rdt: Add Haswell feature discovery Borislav Petkov <bp@suse.de> - 2016-10-09 18:30 +0200
Re: [PATCH v3 07/18] x86/intel_rdt: Add Haswell feature discovery "Luck, Tony" <tony.luck@intel.com> - 2016-10-10 21:00 +0200
Re: [PATCH v3 07/18] x86/intel_rdt: Add Haswell feature discovery Borislav Petkov <bp@suse.de> - 2016-10-11 13:20 +0200
RE: [PATCH v3 07/18] x86/intel_rdt: Add Haswell feature discovery "Luck, Tony" <tony.luck@intel.com> - 2016-10-11 17:00 +0200
[PATCH v3 13/18] x86/intel_rdt: Add mkdir to resctrl file system "Fenghua Yu" <fenghua.yu@intel.com> - 2016-10-08 01:50 +0200
Re: [PATCH v3 13/18] x86/intel_rdt: Add mkdir to resctrl file system Nilay Vaish <nilayvaish@gmail.com> - 2016-10-10 20:00 +0200
[RFC PATCH 19/18] x86/intel_rdt: Add support for L2 cache allocation "Luck, Tony" <tony.luck@intel.com> - 2016-10-08 02:00 +0200
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