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Groups > linux.kernel > #1494430
| From | Sinan Kaya <okaya@codeaurora.org> |
|---|---|
| Newsgroups | linux.kernel |
| Subject | Re: [PATCH V4 05/10] dmaengine: qcom_hidma: make pending_tre_count atomic |
| Date | 2016-10-01 17:20 +0200 |
| Message-ID | <snuf0-1Sl-9@gated-at.bofh.it> (permalink) |
| References | <smz73-6wm-3@gated-at.bofh.it> <smz74-6wm-13@gated-at.bofh.it> <snlOp-4vG-1@gated-at.bofh.it> |
| Organization | linux.* mail to news gateway |
On 10/1/2016 2:19 AM, Vinod Koul wrote: >> Making it atomic so that it can be updated from multiple contexts. > How is it multiple contexts? It's either existing context of MSI, not both! > I was trying to mean multiple processor contexts here. The driver allocates 11 MSI interrupts. Each MSI interrupt can be assigned to a different CPU. Then, we have a race condition for common variables as they share the same interrupt handler with a different cause bit. I will put the above description into the commit text. -- Sinan Kaya Qualcomm Datacenter Technologies, Inc. as an affiliate of Qualcomm Technologies, Inc. Qualcomm Technologies, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project.
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[PATCH V4 05/10] dmaengine: qcom_hidma: make pending_tre_count atomic Sinan Kaya <okaya@codeaurora.org> - 2016-09-29 04:20 +0200
Re: [PATCH V4 05/10] dmaengine: qcom_hidma: make pending_tre_count atomic Vinod Koul <vinod.koul@intel.com> - 2016-10-01 08:20 +0200
Re: [PATCH V4 05/10] dmaengine: qcom_hidma: make pending_tre_count atomic Sinan Kaya <okaya@codeaurora.org> - 2016-10-01 17:20 +0200
Re: [PATCH V4 05/10] dmaengine: qcom_hidma: make pending_tre_count atomic Vinod Koul <vinod.koul@intel.com> - 2016-10-03 05:40 +0200
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