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Re: [PATCH v3 2/3] pinctrl: cherryview: Do not add all southwest and north GPIOs to IRQ domain

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On Tue, Sep 20, 2016 at 2:15 PM, Mika Westerberg
<mika.westerberg@linux.intel.com> wrote:

> It turns out that for north and southwest communities, they can only
> generate GPIO interrupts for lower 8 interrupts (IntSel value). The upper
> part (8-15) can only generate GPEs (General Purpose Events).
>
> Now the reason why EC events such as pressing hotkeys does not work if we
> mask all the interrupts is that in order to generate either interrupts or
> GPEs the INTMASK register must have that particular interrupt unmasked. In
> case of GPEs the CPU does not trigger normal interrupt (and thus the GPIO
> driver does not see it) but instead it causes SCI (System Control
> Interrupt) to be triggered with the GPE in question set.
>
> To make this all work as expected we only add those GPIOs to the IRQ domain
> that can actually generate interrupts (IntSel value 0-7) and skip others.
>
> Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com>

Patch applied, had to merge in the recent fix from -rc6 first but
after that it applied cleanly. Check the result please!

Yours,
Linus Walleij

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[PATCH v3 2/3] pinctrl: cherryview: Do not add all southwest and north GPIOs to IRQ domain Mika Westerberg <mika.westerberg@linux.intel.com> - 2016-09-20 14:20 +0200
  Re: [PATCH v3 2/3] pinctrl: cherryview: Do not add all southwest and  north GPIOs to IRQ domain Linus Walleij <linus.walleij@linaro.org> - 2016-09-23 15:00 +0200
    Re: [PATCH v3 2/3] pinctrl: cherryview: Do not add all southwest and  north GPIOs to IRQ domain Mika Westerberg <mika.westerberg@linux.intel.com> - 2016-09-23 20:10 +0200

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