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Re: [PATCH 01/13] perf/core: Add perf_arch_regs and mask to perf_regs structure

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On Tuesday 06 September 2016 02:40 PM, Peter Zijlstra wrote:
> On Tue, Sep 06, 2016 at 09:55:43AM +0530, Madhavan Srinivasan wrote:
>>
>> On Thursday 01 September 2016 12:56 PM, Peter Zijlstra wrote:
>>> On Mon, Aug 29, 2016 at 02:30:46AM +0530, Madhavan Srinivasan wrote:
>>>> It's a perennial request from hardware folks to be able to
>>>> see the raw values of the pmu registers. Partly it's so that
>>>> they can verify perf is doing what they want, and some
>>>> of it is that they're interested in some of the more obscure
>>>> info that isn't plumbed out through other perf interfaces.
>>> How much and what is that? Can't we try and get interfaces sorted?
>> We have bunch of registers which exports information regarding the
>> sampled instruction like SIER/SIAR/SDAR/MMCRA. Lot of bits in these
>> registers are not yet architected and incase of SIER register, some of
>> the bits are not plumbed out and we are working on getting some these
>> exposed via perf.
> What kind of information is this? I'm not familiar with the Power PMU
> all that much, so you'll have to spell it out, not just mention the
> registers its stuffed in.


Sure. When we profile for sample events,
SIER (Sampled Instruction Event Register) provides additional
information about the sampled event when PMI occurred.

SIER [41:42] indicates whether the SIAR(Sampled instruction address 
registers)
and SDAR (Sampled data address register) are valid for the sampled event.

SIER [46:48] indicates the type of intructions,

001 Load Instruction
010 Store instruction
011 Branch Instruction
100 Floating Point Instruction other than a Load or Store instruction
101 Fixed Point Instruction other than a Load or Store instruction
110 Condition Register or System Call Instruction

SIER[49:51] gives information on the source of the sampled
instruction like instruction came from primary, secondary,
tertiary cache or beyond.

SIER[52:55] provide information on branch type instructions
Like mispredict and cause of it.

SIER[56:59] provides information on translation and also
source of translation like TLB, secondary cache, tertiary
or beyond

SIER[60:62] provides the interesting data on the storage
access like L1/l2/L3... so on.

Most of these could be plumbed out through standard mechanisms
and it's all the other bits that are more interesting, but
these are not architected and not public.

Like wise, MMCRA (Monitor Mode Control Register A) is a
configuration register for sampling and thresholding events.
Provide data on various event configuration information.

Link to the PowerISA v2.07 and Chapters 9 describes in
detail on these registers.

https://www.power.org/wp-content/uploads/2013/05/PowerISA_V2.07_PUBLIC.pdf

Maddy


>

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[PATCH 00/13] Add support for perf_arch_regs Madhavan Srinivasan <maddy@linux.vnet.ibm.com> - 2016-08-28 23:10 +0200
  [PATCH 01/13] perf/core: Add perf_arch_regs and mask to perf_regs structure Madhavan Srinivasan <maddy@linux.vnet.ibm.com> - 2016-08-28 23:10 +0200
    Re: [PATCH 01/13] perf/core: Add perf_arch_regs and mask to  perf_regs structure kbuild test robot <lkp@intel.com> - 2016-08-29 01:50 +0200
    Re: [PATCH 01/13] perf/core: Add perf_arch_regs and mask to  perf_regs structure Peter Zijlstra <peterz@infradead.org> - 2016-09-01 09:30 +0200
      Re: [PATCH 01/13] perf/core: Add perf_arch_regs and mask to perf_regs  structure Madhavan Srinivasan <maddy@linux.vnet.ibm.com> - 2016-09-06 06:30 +0200
        Re: [PATCH 01/13] perf/core: Add perf_arch_regs and mask to  perf_regs structure Peter Zijlstra <peterz@infradead.org> - 2016-09-06 11:20 +0200
          Re: [PATCH 01/13] perf/core: Add perf_arch_regs and mask to perf_regs  structure Madhavan Srinivasan <maddy@linux.vnet.ibm.com> - 2016-09-09 02:50 +0200
  [PATCH 08/13] powerpc/perf: Add support for perf_arch_regs for newer Power processor Madhavan Srinivasan <maddy@linux.vnet.ibm.com> - 2016-08-28 23:10 +0200
  [PATCH 04/13] perf/core: Extend perf_output_sample_regs() to include perf_arch_regs Madhavan Srinivasan <maddy@linux.vnet.ibm.com> - 2016-08-28 23:10 +0200
    Re: [PATCH 04/13] perf/core: Extend perf_output_sample_regs() to  include perf_arch_regs Nilay Vaish <nilayvaish@gmail.com> - 2016-08-30 18:20 +0200
      Re: [PATCH 04/13] perf/core: Extend perf_output_sample_regs() to  include perf_arch_regs Madhavan Srinivasan <maddy@linux.vnet.ibm.com> - 2016-09-01 05:50 +0200
  [PATCH 02/13] perf/core: Extend perf_sample_regs_intr() to include perf_arch_regs update Madhavan Srinivasan <maddy@linux.vnet.ibm.com> - 2016-08-28 23:10 +0200
  [PATCH 12/13] tool/perf: Add perf_arch_reg mask and arch_reg_names structure Madhavan Srinivasan <maddy@linux.vnet.ibm.com> - 2016-08-28 23:10 +0200
  Re: [PATCH 00/13] Add support for perf_arch_regs Nilay Vaish <nilayvaish@gmail.com> - 2016-08-30 18:10 +0200
    Re: [PATCH 00/13] Add support for perf_arch_regs Madhavan Srinivasan <maddy@linux.vnet.ibm.com> - 2016-09-01 05:10 +0200

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