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[PATCH v2 16/33] x86/intel_rdt: Class of service and capacity bitmask management for CDP

From "Fenghua Yu" <fenghua.yu@intel.com>
Newsgroups linux.kernel
Subject [PATCH v2 16/33] x86/intel_rdt: Class of service and capacity bitmask management for CDP
Date 2016-09-08 09:10 +0200
Message-ID <sf1Dc-2F3-19@gated-at.bofh.it> (permalink)
References <sf1tv-2mB-5@gated-at.bofh.it>
Organization linux.* mail to news gateway

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From: Vikas Shivappa <vikas.shivappa@linux.intel.com>

Add support to manage CLOSid(CLass Of Service id) and capacity
bitmask(cbm) for code data prioritization(CDP).

Closid management includes changes to allocating, freeing closid and
closid_get and closid_put and changes to closid availability map during
CDP set up. CDP has a separate cbm for code and data.

Each closid is mapped to a (dcache_cbm, icache_cbm) pair when cdp mode
is enabled.

Signed-off-by: Vikas Shivappa <vikas.shivappa@linux.intel.com>
Signed-off-by: Fenghua Yu <fenghua.yu@intel.com>
Reviewed-by: Tony Luck <tony.luck@intel.com>
---
 arch/x86/kernel/cpu/intel_rdt.c | 24 ++++++++++++++++++++----
 1 file changed, 20 insertions(+), 4 deletions(-)

diff --git a/arch/x86/kernel/cpu/intel_rdt.c b/arch/x86/kernel/cpu/intel_rdt.c
index e0f23b6..9cee3fe 100644
--- a/arch/x86/kernel/cpu/intel_rdt.c
+++ b/arch/x86/kernel/cpu/intel_rdt.c
@@ -27,7 +27,13 @@
 #include <asm/intel_rdt.h>
 
 /*
- * cctable maintains 1:1 mapping between CLOSid and cache bitmask.
+ * During cache alloc mode cctable maintains 1:1 mapping between
+ * CLOSid and cache bitmask.
+ *
+ * During CDP mode, the cctable maintains a 1:2 mapping between the closid
+ * and (dcache_cbm, icache_cbm) pair.
+ * index of a dcache_cbm for CLOSid 'n' = n << 1.
+ * index of a icache_cbm for CLOSid 'n' = n << 1 + 1
  */
 static struct clos_cbm_table *cctable;
 /*
@@ -50,6 +56,13 @@ bool cdp_enabled;
 
 #define __DCBM_TABLE_INDEX(x)	(x << 1)
 #define __ICBM_TABLE_INDEX(x)	((x << 1) + 1)
+#define __DCBM_MSR_INDEX(x)			\
+	CBM_FROM_INDEX(__DCBM_TABLE_INDEX(x))
+#define __ICBM_MSR_INDEX(x)			\
+	CBM_FROM_INDEX(__ICBM_TABLE_INDEX(x))
+
+#define DCBM_TABLE_INDEX(x)	(x << cdp_enabled)
+#define ICBM_TABLE_INDEX(x)	((x << cdp_enabled) + cdp_enabled)
 
 struct rdt_remote_data {
 	int msr;
@@ -107,9 +120,12 @@ void __intel_rdt_sched_in(void *dummy)
 	state->closid = 0;
 }
 
+/*
+ * When cdp mode is enabled, refcnt is maintained in the dcache_cbm entry.
+ */
 static inline void closid_get(u32 closid)
 {
-	struct clos_cbm_table *cct = &cctable[closid];
+	struct clos_cbm_table *cct = &cctable[DCBM_TABLE_INDEX(closid)];
 
 	lockdep_assert_held(&rdtgroup_mutex);
 
@@ -139,7 +155,7 @@ static int closid_alloc(u32 *closid)
 static inline void closid_free(u32 closid)
 {
 	clear_bit(closid, cconfig.closmap);
-	cctable[closid].cbm = 0;
+	cctable[DCBM_TABLE_INDEX(closid)].cbm = 0;
 
 	if (WARN_ON(!cconfig.closids_used))
 		return;
@@ -149,7 +165,7 @@ static inline void closid_free(u32 closid)
 
 static void closid_put(u32 closid)
 {
-	struct clos_cbm_table *cct = &cctable[closid];
+	struct clos_cbm_table *cct = &cctable[DCBM_TABLE_INDEX(closid)];
 
 	lockdep_assert_held(&rdtgroup_mutex);
 	if (WARN_ON(!cct->clos_refcnt))
-- 
2.5.0

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Thread

[PATCH v2 00/33] Enable Intel Resource Allocation in Resource Director Technology  "Fenghua Yu" <fenghua.yu@intel.com> - 2016-09-08 09:00 +0200
  [PATCH v2 32/33] MAINTAINERS: Add maintainer for Intel RDT resource allocation "Fenghua Yu" <fenghua.yu@intel.com> - 2016-09-08 09:00 +0200
  [PATCH v2 30/33] x86/intel_rdt_rdtgroup.c: Process schemata input from resctrl interface "Fenghua Yu" <fenghua.yu@intel.com> - 2016-09-08 09:00 +0200
    Re: [PATCH v2 30/33] x86/intel_rdt_rdtgroup.c: Process schemata  input from resctrl interface Thomas Gleixner <tglx@linutronix.de> - 2016-09-09 00:30 +0200
  [PATCH v2 31/33] Documentation/kernel-parameters: Add kernel parameter "resctrl" for CAT "Fenghua Yu" <fenghua.yu@intel.com> - 2016-09-08 09:00 +0200
    Re: [PATCH v2 31/33] Documentation/kernel-parameters: Add kernel  parameter "resctrl" for CAT Thomas Gleixner <tglx@linutronix.de> - 2016-09-09 00:30 +0200
  [PATCH v2 28/33] x86/intel_rdt_rdtgroup.c: Read and write cpus "Fenghua Yu" <fenghua.yu@intel.com> - 2016-09-08 09:10 +0200
    Re: [PATCH v2 28/33] x86/intel_rdt_rdtgroup.c: Read and write cpus Thomas Gleixner <tglx@linutronix.de> - 2016-09-08 22:30 +0200
  [PATCH v2 24/33] x86/intel_rdt_rdtgroup.c: Create info directory "Fenghua Yu" <fenghua.yu@intel.com> - 2016-09-08 09:10 +0200
    Re: [PATCH v2 24/33] x86/intel_rdt_rdtgroup.c: Create info  directory Thomas Gleixner <tglx@linutronix.de> - 2016-09-08 18:10 +0200
  [PATCH v2 11/33] x86/intel_rdt: Hot cpu support for Cache Allocation "Fenghua Yu" <fenghua.yu@intel.com> - 2016-09-08 09:10 +0200
    Re: [PATCH v2 11/33] x86/intel_rdt: Hot cpu support for Cache  Allocation Thomas Gleixner <tglx@linutronix.de> - 2016-09-08 12:10 +0200
  [PATCH v2 13/33] Define CONFIG_INTEL_RDT "Fenghua Yu" <fenghua.yu@intel.com> - 2016-09-08 09:10 +0200
    Re: [PATCH v2 13/33] Define CONFIG_INTEL_RDT Thomas Gleixner <tglx@linutronix.de> - 2016-09-08 12:20 +0200
  [PATCH v2 08/33] x86/intel_rdt: Add Class of service management "Fenghua Yu" <fenghua.yu@intel.com> - 2016-09-08 09:10 +0200
    Re: [PATCH v2 08/33] x86/intel_rdt: Add Class of service  management Thomas Gleixner <tglx@linutronix.de> - 2016-09-08 11:00 +0200
  [PATCH v2 22/33] x86/intel_rdt.c: Extend RDT to per cache and per resources "Fenghua Yu" <fenghua.yu@intel.com> - 2016-09-08 09:10 +0200
    Re: [PATCH v2 22/33] x86/intel_rdt.c: Extend RDT to per cache and  per resources Thomas Gleixner <tglx@linutronix.de> - 2016-09-08 17:10 +0200
  [PATCH v2 20/33] x86/intel_rdt.h: Header for inter_rdt.c "Fenghua Yu" <fenghua.yu@intel.com> - 2016-09-08 09:10 +0200
    Re: [PATCH v2 20/33] x86/intel_rdt.h: Header for inter_rdt.c Thomas Gleixner <tglx@linutronix.de> - 2016-09-08 14:40 +0200
  [PATCH v2 10/33] x86/intel_rdt: Implement scheduling support for Intel RDT "Fenghua Yu" <fenghua.yu@intel.com> - 2016-09-08 09:10 +0200
    Re: [PATCH v2 10/33] x86/intel_rdt: Implement scheduling support  for Intel RDT Thomas Gleixner <tglx@linutronix.de> - 2016-09-08 12:00 +0200
  [PATCH v2 16/33] x86/intel_rdt: Class of service and capacity bitmask management for CDP "Fenghua Yu" <fenghua.yu@intel.com> - 2016-09-08 09:10 +0200
    Re: [PATCH v2 16/33] x86/intel_rdt: Class of service and capacity  bitmask management for CDP Thomas Gleixner <tglx@linutronix.de> - 2016-09-08 12:40 +0200
  [PATCH v2 04/33] drivers/base/cacheinfo.c: Export some cacheinfo functions for others to use "Fenghua Yu" <fenghua.yu@intel.com> - 2016-09-08 09:10 +0200
    Re: [PATCH v2 04/33] drivers/base/cacheinfo.c: Export some cacheinfo  functions for others to use Thomas Gleixner <tglx@linutronix.de> - 2016-09-08 10:30 +0200
  [PATCH v2 25/33] include/linux/resctrl.h: Define fork and exit functions in a new header file "Fenghua Yu" <fenghua.yu@intel.com> - 2016-09-08 09:10 +0200
    Re: [PATCH v2 25/33] include/linux/resctrl.h: Define fork and exit  functions in a new header file Thomas Gleixner <tglx@linutronix.de> - 2016-09-08 18:20 +0200
  [PATCH v2 27/33] x86/intel_rdt_rdtgroup.c: Implement resctrl file system commands "Fenghua Yu" <fenghua.yu@intel.com> - 2016-09-08 09:10 +0200
    Re: [PATCH v2 27/33] x86/intel_rdt_rdtgroup.c: Implement resctrl  file system commands Thomas Gleixner <tglx@linutronix.de> - 2016-09-08 22:20 +0200
    Re: [PATCH v2 27/33] x86/intel_rdt_rdtgroup.c: Implement resctrl  file system commands Fenghua Yu <fenghua.yu@intel.com> - 2016-09-09 00:30 +0200
  [PATCH v2 29/33] x86/intel_rdt_rdtgroup.c: Tasks iterator and write "Fenghua Yu" <fenghua.yu@intel.com> - 2016-09-08 09:10 +0200
    Re: [PATCH v2 29/33] x86/intel_rdt_rdtgroup.c: Tasks iterator and  write Thomas Gleixner <tglx@linutronix.de> - 2016-09-08 23:00 +0200
  [PATCH v2 17/33] x86/intel_rdt: Hot cpu update for code data prioritization "Fenghua Yu" <fenghua.yu@intel.com> - 2016-09-08 09:10 +0200
    Re: [PATCH v2 17/33] x86/intel_rdt: Hot cpu update for code data  prioritization Thomas Gleixner <tglx@linutronix.de> - 2016-09-08 12:40 +0200
  [PATCH v2 06/33] Documentation, x86: Documentation for Intel resource allocation user interface "Fenghua Yu" <fenghua.yu@intel.com> - 2016-09-08 09:10 +0200
    Re: [PATCH v2 06/33] Documentation, x86: Documentation for Intel  resource allocation user interface Borislav Petkov <bp@suse.de> - 2016-09-08 13:30 +0200
    Re: [PATCH v2 06/33] Documentation, x86: Documentation for Intel  resource allocation user interface Fenghua Yu <fenghua.yu@intel.com> - 2016-09-09 00:20 +0200
      Re: [PATCH v2 06/33] Documentation, x86: Documentation for Intel  resource allocation user interface Fenghua Yu <fenghua.yu@intel.com> - 2016-09-09 06:30 +0200
  [PATCH v2 03/33] x86, intel_cacheinfo: Enable cache id in x86 "Fenghua Yu" <fenghua.yu@intel.com> - 2016-09-08 09:10 +0200
  [PATCH v2 09/33] x86/intel_rdt: Add L3 cache capacity bitmask management "Fenghua Yu" <fenghua.yu@intel.com> - 2016-09-08 09:10 +0200
    Re: [PATCH v2 09/33] x86/intel_rdt: Add L3 cache capacity bitmask  management Thomas Gleixner <tglx@linutronix.de> - 2016-09-08 11:50 +0200
  [PATCH v2 07/33] x86/intel_rdt: Add support for Cache Allocation detection "Fenghua Yu" <fenghua.yu@intel.com> - 2016-09-08 09:10 +0200
    Re: [PATCH v2 07/33] x86/intel_rdt: Add support for Cache Allocation  detection Borislav Petkov <bp@suse.de> - 2016-09-08 14:00 +0200
      RE: [PATCH v2 07/33] x86/intel_rdt: Add support for Cache  Allocation detection "Yu, Fenghua" <fenghua.yu@intel.com> - 2016-09-08 19:00 +0200
        Re: [PATCH v2 07/33] x86/intel_rdt: Add support for Cache Allocation  detection Borislav Petkov <bp@suse.de> - 2016-09-08 19:20 +0200
    Re: [PATCH v2 07/33] x86/intel_rdt: Add support for Cache Allocation  detection Thomas Gleixner <tglx@linutronix.de> - 2016-09-08 15:20 +0200
      RE: [PATCH v2 07/33] x86/intel_rdt: Add support for Cache  Allocation detection "Yu, Fenghua" <fenghua.yu@intel.com> - 2016-09-08 16:00 +0200
  [PATCH v2 01/33] cacheinfo: Introduce cache id "Fenghua Yu" <fenghua.yu@intel.com> - 2016-09-08 09:10 +0200
  [PATCH v2 05/33] x86/intel_rdt: Cache Allocation documentation "Fenghua Yu" <fenghua.yu@intel.com> - 2016-09-08 09:10 +0200
  [PATCH v2 19/33] magic number for resctrl file system "Fenghua Yu" <fenghua.yu@intel.com> - 2016-09-08 09:10 +0200
    Re: [PATCH v2 19/33] magic number for resctrl file system Thomas Gleixner <tglx@linutronix.de> - 2016-09-08 12:50 +0200
      Re: [PATCH v2 19/33] magic number for resctrl file system Borislav Petkov <bp@alien8.de> - 2016-09-08 12:50 +0200
  [PATCH v2 21/33] x86/intel_rdt_rdtgroup.h: Header for user interface "Fenghua Yu" <fenghua.yu@intel.com> - 2016-09-08 09:10 +0200
    Re: [PATCH v2 21/33] x86/intel_rdt_rdtgroup.h: Header for user  interface Thomas Gleixner <tglx@linutronix.de> - 2016-09-08 14:50 +0200
  [PATCH v2 26/33] Task fork and exit for rdtgroup "Fenghua Yu" <fenghua.yu@intel.com> - 2016-09-08 09:10 +0200
    Re: [PATCH v2 26/33] Task fork and exit for rdtgroup Thomas Gleixner <tglx@linutronix.de> - 2016-09-08 21:50 +0200
  [PATCH v2 18/33] sched.h: Add rg_list and rdtgroup in task_struct "Fenghua Yu" <fenghua.yu@intel.com> - 2016-09-08 09:10 +0200
    Re: [PATCH v2 18/33] sched.h: Add rg_list and rdtgroup in  task_struct Thomas Gleixner <tglx@linutronix.de> - 2016-09-08 12:40 +0200
  [PATCH v2 02/33] Documentation, ABI: Add a document entry for cache id "Fenghua Yu" <fenghua.yu@intel.com> - 2016-09-08 09:10 +0200
    Re: [PATCH v2 02/33] Documentation, ABI: Add a document entry for  cache id Thomas Gleixner <tglx@linutronix.de> - 2016-09-08 21:40 +0200
  [PATCH v2 12/33] x86/intel_rdt: Intel haswell Cache Allocation enumeration "Fenghua Yu" <fenghua.yu@intel.com> - 2016-09-08 09:10 +0200
    Re: [PATCH v2 12/33] x86/intel_rdt: Intel haswell Cache Allocation  enumeration Thomas Gleixner <tglx@linutronix.de> - 2016-09-08 12:20 +0200

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