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Groups > linux.kernel > #1478835
| From | "Fenghua Yu" <fenghua.yu@intel.com> |
|---|---|
| Newsgroups | linux.kernel |
| Subject | [PATCH v2 20/33] x86/intel_rdt.h: Header for inter_rdt.c |
| Date | 2016-09-08 09:10 +0200 |
| Message-ID | <sf1Dc-2F3-13@gated-at.bofh.it> (permalink) |
| References | <sf1tv-2mB-5@gated-at.bofh.it> |
| Organization | linux.* mail to news gateway |
From: Fenghua Yu <fenghua.yu@intel.com>
The header mainly provides functions to call from the user interface
file intel_rdt_rdtgroup.c.
Signed-off-by: Fenghua Yu <fenghua.yu@intel.com>
Reviewed-by: Tony Luck <tony.luck@intel.com>
---
arch/x86/include/asm/intel_rdt.h | 77 +++++++++++++++++++++++++++++++++++++---
1 file changed, 72 insertions(+), 5 deletions(-)
diff --git a/arch/x86/include/asm/intel_rdt.h b/arch/x86/include/asm/intel_rdt.h
index 4e05c6e..a4f794b 100644
--- a/arch/x86/include/asm/intel_rdt.h
+++ b/arch/x86/include/asm/intel_rdt.h
@@ -3,27 +3,94 @@
#ifdef CONFIG_INTEL_RDT
+#include <linux/seq_file.h>
#include <linux/jump_label.h>
-#define MAX_CBM_LENGTH 32
#define IA32_L3_CBM_BASE 0xc90
-#define CBM_FROM_INDEX(x) (IA32_L3_CBM_BASE + x)
-#define MSR_IA32_PQOS_CFG 0xc81
+#define L3_CBM_FROM_INDEX(x) (IA32_L3_CBM_BASE + x)
+
+#define MSR_IA32_L3_QOS_CFG 0xc81
+
+enum resource_type {
+ RESOURCE_L3 = 0,
+ RESOURCE_NUM = 1,
+};
+
+#define MAX_CACHE_LEAVES 4
+#define MAX_CACHE_DOMAINS 64
+
+DECLARE_PER_CPU_READ_MOSTLY(int, cpu_l3_domain);
+DECLARE_PER_CPU_READ_MOSTLY(struct rdtgroup *, cpu_rdtgroup);
extern struct static_key rdt_enable_key;
void __intel_rdt_sched_in(void *dummy);
+extern bool cdp_enabled;
+
+struct rdt_opts {
+ bool cdp_enabled;
+ bool verbose;
+ bool simulate_cat_l3;
+};
+
+struct cache_domain {
+ cpumask_t shared_cpu_map[MAX_CACHE_DOMAINS];
+ unsigned int max_cache_domains_num;
+ unsigned int level;
+ unsigned int shared_cache_id[MAX_CACHE_DOMAINS];
+};
+
+extern struct rdt_opts rdt_opts;
+
struct clos_cbm_table {
unsigned long cbm;
unsigned int clos_refcnt;
};
struct clos_config {
- unsigned long *closmap;
+ unsigned long **closmap;
u32 max_closid;
- u32 closids_used;
};
+struct shared_domain {
+ struct cpumask cpumask;
+ int l3_domain;
+};
+
+#define for_each_cache_domain(domain, start_domain, max_domain) \
+ for (domain = start_domain; domain < max_domain; domain++)
+
+extern struct clos_config cconfig;
+extern struct shared_domain *shared_domain;
+extern int shared_domain_num;
+
+extern struct rdtgroup *root_rdtgrp;
+
+extern struct clos_cbm_table **l3_cctable;
+
+extern unsigned int min_bitmask_len;
+extern void msr_cpu_update(void *arg);
+extern inline void closid_get(u32 closid, int domain);
+extern void closid_put(u32 closid, int domain);
+extern void closid_free(u32 closid, int domain, int level);
+extern int closid_alloc(u32 *closid, int domain);
+extern bool cat_l3_enabled;
+extern unsigned int get_domain_num(int level);
+extern struct shared_domain *shared_domain;
+extern int shared_domain_num;
+extern inline int get_dcbm_table_index(int x);
+extern inline int get_icbm_table_index(int x);
+
+extern int get_cache_leaf(int level, int cpu);
+
+extern void cbm_update_l3_msr(void *pindex);
+extern int level_to_leaf(int level);
+
+extern void init_msrs(bool cdpenabled);
+extern bool cat_enabled(int level);
+extern u64 max_cbm(int level);
+extern u32 max_cbm_len(int level);
+
/*
* intel_rdt_sched_in() - Writes the task's CLOSid to IA32_PQR_MSR
*
--
2.5.0
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[PATCH v2 00/33] Enable Intel Resource Allocation in Resource Director Technology "Fenghua Yu" <fenghua.yu@intel.com> - 2016-09-08 09:00 +0200
[PATCH v2 32/33] MAINTAINERS: Add maintainer for Intel RDT resource allocation "Fenghua Yu" <fenghua.yu@intel.com> - 2016-09-08 09:00 +0200
[PATCH v2 30/33] x86/intel_rdt_rdtgroup.c: Process schemata input from resctrl interface "Fenghua Yu" <fenghua.yu@intel.com> - 2016-09-08 09:00 +0200
Re: [PATCH v2 30/33] x86/intel_rdt_rdtgroup.c: Process schemata input from resctrl interface Thomas Gleixner <tglx@linutronix.de> - 2016-09-09 00:30 +0200
[PATCH v2 31/33] Documentation/kernel-parameters: Add kernel parameter "resctrl" for CAT "Fenghua Yu" <fenghua.yu@intel.com> - 2016-09-08 09:00 +0200
Re: [PATCH v2 31/33] Documentation/kernel-parameters: Add kernel parameter "resctrl" for CAT Thomas Gleixner <tglx@linutronix.de> - 2016-09-09 00:30 +0200
[PATCH v2 28/33] x86/intel_rdt_rdtgroup.c: Read and write cpus "Fenghua Yu" <fenghua.yu@intel.com> - 2016-09-08 09:10 +0200
Re: [PATCH v2 28/33] x86/intel_rdt_rdtgroup.c: Read and write cpus Thomas Gleixner <tglx@linutronix.de> - 2016-09-08 22:30 +0200
[PATCH v2 24/33] x86/intel_rdt_rdtgroup.c: Create info directory "Fenghua Yu" <fenghua.yu@intel.com> - 2016-09-08 09:10 +0200
Re: [PATCH v2 24/33] x86/intel_rdt_rdtgroup.c: Create info directory Thomas Gleixner <tglx@linutronix.de> - 2016-09-08 18:10 +0200
[PATCH v2 11/33] x86/intel_rdt: Hot cpu support for Cache Allocation "Fenghua Yu" <fenghua.yu@intel.com> - 2016-09-08 09:10 +0200
Re: [PATCH v2 11/33] x86/intel_rdt: Hot cpu support for Cache Allocation Thomas Gleixner <tglx@linutronix.de> - 2016-09-08 12:10 +0200
[PATCH v2 13/33] Define CONFIG_INTEL_RDT "Fenghua Yu" <fenghua.yu@intel.com> - 2016-09-08 09:10 +0200
Re: [PATCH v2 13/33] Define CONFIG_INTEL_RDT Thomas Gleixner <tglx@linutronix.de> - 2016-09-08 12:20 +0200
[PATCH v2 08/33] x86/intel_rdt: Add Class of service management "Fenghua Yu" <fenghua.yu@intel.com> - 2016-09-08 09:10 +0200
Re: [PATCH v2 08/33] x86/intel_rdt: Add Class of service management Thomas Gleixner <tglx@linutronix.de> - 2016-09-08 11:00 +0200
[PATCH v2 22/33] x86/intel_rdt.c: Extend RDT to per cache and per resources "Fenghua Yu" <fenghua.yu@intel.com> - 2016-09-08 09:10 +0200
Re: [PATCH v2 22/33] x86/intel_rdt.c: Extend RDT to per cache and per resources Thomas Gleixner <tglx@linutronix.de> - 2016-09-08 17:10 +0200
[PATCH v2 20/33] x86/intel_rdt.h: Header for inter_rdt.c "Fenghua Yu" <fenghua.yu@intel.com> - 2016-09-08 09:10 +0200
Re: [PATCH v2 20/33] x86/intel_rdt.h: Header for inter_rdt.c Thomas Gleixner <tglx@linutronix.de> - 2016-09-08 14:40 +0200
[PATCH v2 10/33] x86/intel_rdt: Implement scheduling support for Intel RDT "Fenghua Yu" <fenghua.yu@intel.com> - 2016-09-08 09:10 +0200
Re: [PATCH v2 10/33] x86/intel_rdt: Implement scheduling support for Intel RDT Thomas Gleixner <tglx@linutronix.de> - 2016-09-08 12:00 +0200
[PATCH v2 16/33] x86/intel_rdt: Class of service and capacity bitmask management for CDP "Fenghua Yu" <fenghua.yu@intel.com> - 2016-09-08 09:10 +0200
Re: [PATCH v2 16/33] x86/intel_rdt: Class of service and capacity bitmask management for CDP Thomas Gleixner <tglx@linutronix.de> - 2016-09-08 12:40 +0200
[PATCH v2 04/33] drivers/base/cacheinfo.c: Export some cacheinfo functions for others to use "Fenghua Yu" <fenghua.yu@intel.com> - 2016-09-08 09:10 +0200
Re: [PATCH v2 04/33] drivers/base/cacheinfo.c: Export some cacheinfo functions for others to use Thomas Gleixner <tglx@linutronix.de> - 2016-09-08 10:30 +0200
[PATCH v2 25/33] include/linux/resctrl.h: Define fork and exit functions in a new header file "Fenghua Yu" <fenghua.yu@intel.com> - 2016-09-08 09:10 +0200
Re: [PATCH v2 25/33] include/linux/resctrl.h: Define fork and exit functions in a new header file Thomas Gleixner <tglx@linutronix.de> - 2016-09-08 18:20 +0200
[PATCH v2 27/33] x86/intel_rdt_rdtgroup.c: Implement resctrl file system commands "Fenghua Yu" <fenghua.yu@intel.com> - 2016-09-08 09:10 +0200
Re: [PATCH v2 27/33] x86/intel_rdt_rdtgroup.c: Implement resctrl file system commands Thomas Gleixner <tglx@linutronix.de> - 2016-09-08 22:20 +0200
Re: [PATCH v2 27/33] x86/intel_rdt_rdtgroup.c: Implement resctrl file system commands Fenghua Yu <fenghua.yu@intel.com> - 2016-09-09 00:30 +0200
[PATCH v2 29/33] x86/intel_rdt_rdtgroup.c: Tasks iterator and write "Fenghua Yu" <fenghua.yu@intel.com> - 2016-09-08 09:10 +0200
Re: [PATCH v2 29/33] x86/intel_rdt_rdtgroup.c: Tasks iterator and write Thomas Gleixner <tglx@linutronix.de> - 2016-09-08 23:00 +0200
[PATCH v2 17/33] x86/intel_rdt: Hot cpu update for code data prioritization "Fenghua Yu" <fenghua.yu@intel.com> - 2016-09-08 09:10 +0200
Re: [PATCH v2 17/33] x86/intel_rdt: Hot cpu update for code data prioritization Thomas Gleixner <tglx@linutronix.de> - 2016-09-08 12:40 +0200
[PATCH v2 06/33] Documentation, x86: Documentation for Intel resource allocation user interface "Fenghua Yu" <fenghua.yu@intel.com> - 2016-09-08 09:10 +0200
Re: [PATCH v2 06/33] Documentation, x86: Documentation for Intel resource allocation user interface Borislav Petkov <bp@suse.de> - 2016-09-08 13:30 +0200
Re: [PATCH v2 06/33] Documentation, x86: Documentation for Intel resource allocation user interface Fenghua Yu <fenghua.yu@intel.com> - 2016-09-09 00:20 +0200
Re: [PATCH v2 06/33] Documentation, x86: Documentation for Intel resource allocation user interface Fenghua Yu <fenghua.yu@intel.com> - 2016-09-09 06:30 +0200
[PATCH v2 03/33] x86, intel_cacheinfo: Enable cache id in x86 "Fenghua Yu" <fenghua.yu@intel.com> - 2016-09-08 09:10 +0200
[PATCH v2 09/33] x86/intel_rdt: Add L3 cache capacity bitmask management "Fenghua Yu" <fenghua.yu@intel.com> - 2016-09-08 09:10 +0200
Re: [PATCH v2 09/33] x86/intel_rdt: Add L3 cache capacity bitmask management Thomas Gleixner <tglx@linutronix.de> - 2016-09-08 11:50 +0200
[PATCH v2 07/33] x86/intel_rdt: Add support for Cache Allocation detection "Fenghua Yu" <fenghua.yu@intel.com> - 2016-09-08 09:10 +0200
Re: [PATCH v2 07/33] x86/intel_rdt: Add support for Cache Allocation detection Borislav Petkov <bp@suse.de> - 2016-09-08 14:00 +0200
RE: [PATCH v2 07/33] x86/intel_rdt: Add support for Cache Allocation detection "Yu, Fenghua" <fenghua.yu@intel.com> - 2016-09-08 19:00 +0200
Re: [PATCH v2 07/33] x86/intel_rdt: Add support for Cache Allocation detection Borislav Petkov <bp@suse.de> - 2016-09-08 19:20 +0200
Re: [PATCH v2 07/33] x86/intel_rdt: Add support for Cache Allocation detection Thomas Gleixner <tglx@linutronix.de> - 2016-09-08 15:20 +0200
RE: [PATCH v2 07/33] x86/intel_rdt: Add support for Cache Allocation detection "Yu, Fenghua" <fenghua.yu@intel.com> - 2016-09-08 16:00 +0200
[PATCH v2 01/33] cacheinfo: Introduce cache id "Fenghua Yu" <fenghua.yu@intel.com> - 2016-09-08 09:10 +0200
[PATCH v2 05/33] x86/intel_rdt: Cache Allocation documentation "Fenghua Yu" <fenghua.yu@intel.com> - 2016-09-08 09:10 +0200
[PATCH v2 19/33] magic number for resctrl file system "Fenghua Yu" <fenghua.yu@intel.com> - 2016-09-08 09:10 +0200
Re: [PATCH v2 19/33] magic number for resctrl file system Thomas Gleixner <tglx@linutronix.de> - 2016-09-08 12:50 +0200
Re: [PATCH v2 19/33] magic number for resctrl file system Borislav Petkov <bp@alien8.de> - 2016-09-08 12:50 +0200
[PATCH v2 21/33] x86/intel_rdt_rdtgroup.h: Header for user interface "Fenghua Yu" <fenghua.yu@intel.com> - 2016-09-08 09:10 +0200
Re: [PATCH v2 21/33] x86/intel_rdt_rdtgroup.h: Header for user interface Thomas Gleixner <tglx@linutronix.de> - 2016-09-08 14:50 +0200
[PATCH v2 26/33] Task fork and exit for rdtgroup "Fenghua Yu" <fenghua.yu@intel.com> - 2016-09-08 09:10 +0200
Re: [PATCH v2 26/33] Task fork and exit for rdtgroup Thomas Gleixner <tglx@linutronix.de> - 2016-09-08 21:50 +0200
[PATCH v2 18/33] sched.h: Add rg_list and rdtgroup in task_struct "Fenghua Yu" <fenghua.yu@intel.com> - 2016-09-08 09:10 +0200
Re: [PATCH v2 18/33] sched.h: Add rg_list and rdtgroup in task_struct Thomas Gleixner <tglx@linutronix.de> - 2016-09-08 12:40 +0200
[PATCH v2 02/33] Documentation, ABI: Add a document entry for cache id "Fenghua Yu" <fenghua.yu@intel.com> - 2016-09-08 09:10 +0200
Re: [PATCH v2 02/33] Documentation, ABI: Add a document entry for cache id Thomas Gleixner <tglx@linutronix.de> - 2016-09-08 21:40 +0200
[PATCH v2 12/33] x86/intel_rdt: Intel haswell Cache Allocation enumeration "Fenghua Yu" <fenghua.yu@intel.com> - 2016-09-08 09:10 +0200
Re: [PATCH v2 12/33] x86/intel_rdt: Intel haswell Cache Allocation enumeration Thomas Gleixner <tglx@linutronix.de> - 2016-09-08 12:20 +0200
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