Re: [PATCH v3 9/9] arm64: Work around systems with mismatched cache line sizes

From	Suzuki K Poulose <Suzuki.Poulose@arm.com>
Newsgroups	linux.kernel
Subject	Re: [PATCH v3 9/9] arm64: Work around systems with mismatched cache line sizes
Date	2016-09-05 12:30 +0200
Message-ID	<sdZk5-2uu-17@gated-at.bofh.it> (permalink)
References	<sdYR4-209-39@gated-at.bofh.it> <sdZ0K-2iZ-49@gated-at.bofh.it> <sdZaq-2o0-17@gated-at.bofh.it>
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On 05/09/16 11:10, Ard Biesheuvel wrote:
> On 5 September 2016 at 10:58, Suzuki K Poulose <suzuki.poulose@arm.com> wrote:
>> +/*
>> + * read_ctr - read CTR_EL0. If the system has mismatched
>> + * cache line sizes, provide the system wide safe value.
>> + */
>> +       .macro  read_ctr, reg
>> +alternative_if_not ARM64_MISMATCHED_CACHE_LINE_SIZE
>> +       mrs     \reg, ctr_el0                   // read CTR
>> +       nop
>> +       nop
>> +alternative_else
>> +       adr_l   \reg, arm64_ftr_reg_ctrel0      // Read system wide safe CTR value
>> +       ldr     \reg, [\reg, #ARM64_FTR_SYSVAL] // from arm64_ftr_reg_ctrel0.sys_val
>
> You should be able to use
>
> ldr_l \reg, arm64_ftr_reg_ctrel0 + ARM64_FTR_SYSVAL
>
> here, and save one instruction.

I had given a thought about that and chose the above to account for a
rare chance of arm64_ftr_reg_ctrel0 spanning across a 4K boundary. But,
you are right, ldr_l could treat (arm64_ftr_reg_ctrel0 + ARM64_FTR_SYSVAL)
as the symbol address and still get the right offset.

Suzuki

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[PATCH v3 0/9] arm64: Work around for mismatched cache line size Suzuki K Poulose <suzuki.poulose@arm.com> - 2016-09-05 12:00 +0200
  [PATCH v3 5/9] arm64: insn: Add helpers for adrp offsets Suzuki K Poulose <suzuki.poulose@arm.com> - 2016-09-05 12:00 +0200
  [PATCH v3 1/9] arm64: Set the safe value for L1 icache policy Suzuki K Poulose <suzuki.poulose@arm.com> - 2016-09-05 12:10 +0200
  [PATCH v3 8/9] arm64: Refactor sysinstr exception handling Suzuki K Poulose <suzuki.poulose@arm.com> - 2016-09-05 12:10 +0200
    Re: [PATCH v3 8/9] arm64: Refactor sysinstr exception handling Will Deacon <will.deacon@arm.com> - 2016-09-07 10:50 +0200
    Re: [PATCH v3 8/9] arm64: Refactor sysinstr exception handling Andre Przywara <andre.przywara@arm.com> - 2016-09-07 13:40 +0200
  [PATCH v3 3/9] arm64: Rearrange CPU errata workaround checks Suzuki K Poulose <suzuki.poulose@arm.com> - 2016-09-05 12:10 +0200
  [PATCH v3 2/9] arm64: Use consistent naming for errata handling Suzuki K Poulose <suzuki.poulose@arm.com> - 2016-09-05 12:10 +0200
    Re: [PATCH v3 2/9] arm64: Use consistent naming for errata handling Andre Przywara <andre.przywara@arm.com> - 2016-09-07 12:40 +0200
  [PATCH v3 9/9] arm64: Work around systems with mismatched cache line sizes Suzuki K Poulose <suzuki.poulose@arm.com> - 2016-09-05 12:10 +0200
    Re: [PATCH v3 9/9] arm64: Work around systems with mismatched cache  line sizes Ard Biesheuvel <ard.biesheuvel@linaro.org> - 2016-09-05 12:20 +0200
      Re: [PATCH v3 9/9] arm64: Work around systems with mismatched cache  line sizes Suzuki K Poulose <Suzuki.Poulose@arm.com> - 2016-09-05 12:30 +0200

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