Re: [PATCH v3 7/9] arm64: cpufeature: Track user visible fields

From	Suzuki K Poulose <Suzuki.Poulose@arm.com>
Newsgroups	linux.kernel
Subject	Re: [PATCH v3 7/9] arm64: cpufeature: Track user visible fields
Date	2017-01-06 12:20 +0100
Message-ID	<sWAIV-100-15@gated-at.bofh.it> (permalink)
References	<sVYNk-8qL-3@gated-at.bofh.it> <sVYNl-8qL-53@gated-at.bofh.it> <sWkEa-6xP-21@gated-at.bofh.it>
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On 05/01/17 18:06, Catalin Marinas wrote:
> On Wed, Jan 04, 2017 at 05:49:05PM +0000, Suzuki K. Poulose wrote:
>> Track the user visible fields of a CPU feature register. This will be
>> used for exposing the value to the userspace. All the user visible
>> fields of a feature register will be passed on as it is, while the
>> others would be filled with their respective safe value.
>>
>> Cc: Catalin Marinas <catalin.marinas@arm.com>
>> Cc: Will Deacon <will.deacon@arm.com>
>> Cc: Mark Rutland <mark.rutland@arm.com>
>> Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
>
> Reviewed-by: Catalin Marinas <catalin.marinas@arm.com>
>
>> @@ -81,75 +82,75 @@ cpufeature_pan_not_uao(const struct arm64_cpu_capabilities *entry, int __unused)
>>
>>
>>  static const struct arm64_ftr_bits ftr_id_aa64isar0[] = {
>> -	ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64ISAR0_RDM_SHIFT, 4, 0),
>> -	ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_ATOMICS_SHIFT, 4, 0),
>> -	ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_CRC32_SHIFT, 4, 0),
>> -	ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SHA2_SHIFT, 4, 0),
>> -	ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SHA1_SHIFT, 4, 0),
>> -	ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_AES_SHIFT, 4, 0),
>> +	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, ID_AA64ISAR0_RDM_SHIFT, 4, 0),

On a second look, I think we should make the RDM field visible to the user space as it
is something useful for the user.

>> +	ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_ATOMICS_SHIFT, 4, 0),
>> +	ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_CRC32_SHIFT, 4, 0),
>> +	ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SHA2_SHIFT, 4, 0),
>> +	ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SHA1_SHIFT, 4, 0),
>> +	ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_AES_SHIFT, 4, 0),
>
> BTW, as a separate patch I think we need to expose the RDM field in this
> register as well, together with a corresponding HWCAP bit.

OK, I will send a separate patch for this.

Thanks for the review.

Suzuki

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[PATCH v3 0/9] arm64: Expose CPUID registers via emulation Suzuki K Poulose <suzuki.poulose@arm.com> - 2017-01-04 19:50 +0100
  [PATCH v3 6/9] arm64: Add helper to decode register from instruction Suzuki K Poulose <suzuki.poulose@arm.com> - 2017-01-04 19:50 +0100
    Re: [PATCH v3 6/9] arm64: Add helper to decode register from  instruction Catalin Marinas <catalin.marinas@arm.com> - 2017-01-05 18:50 +0100
  [PATCH v3 8/9] arm64: cpufeature: Expose CPUID registers by emulation Suzuki K Poulose <suzuki.poulose@arm.com> - 2017-01-04 19:50 +0100
    Re: [PATCH v3 8/9] arm64: cpufeature: Expose CPUID registers by  emulation Catalin Marinas <catalin.marinas@arm.com> - 2017-01-05 19:40 +0100
  [PATCH v3 4/9] arm64: cpufeature: Document the rules of safe value for features Suzuki K Poulose <suzuki.poulose@arm.com> - 2017-01-04 19:50 +0100
    Re: [PATCH v3 4/9] arm64: cpufeature: Document the rules of safe  value for features Catalin Marinas <catalin.marinas@arm.com> - 2017-01-06 13:40 +0100
      Re: [PATCH v3 4/9] arm64: cpufeature: Document the rules of safe  value for features Suzuki K Poulose <Suzuki.Poulose@arm.com> - 2017-01-09 11:50 +0100
        Re: [PATCH v3 4/9] arm64: cpufeature: Document the rules of safe  value for features Catalin Marinas <catalin.marinas@arm.com> - 2017-01-09 13:10 +0100
  [PATCH v3 9/9] arm64: Documentation - Expose CPU feature registers Suzuki K Poulose <suzuki.poulose@arm.com> - 2017-01-04 19:50 +0100
    Re: [PATCH v3 9/9] arm64: Documentation - Expose CPU feature  registers Catalin Marinas <catalin.marinas@arm.com> - 2017-01-06 13:20 +0100
      Re: [PATCH v3 9/9] arm64: Documentation - Expose CPU feature  registers Suzuki K Poulose <Suzuki.Poulose@arm.com> - 2017-01-09 12:10 +0100
  [PATCH v3 2/9] arm64: cpufeature: remove explicit RAZ fields Suzuki K Poulose <suzuki.poulose@arm.com> - 2017-01-04 19:50 +0100
    Re: [PATCH v3 2/9] arm64: cpufeature: remove explicit RAZ fields Catalin Marinas <catalin.marinas@arm.com> - 2017-01-05 18:20 +0100
  [PATCH v3 1/9] arm64: cpufeature: treat unknown fields as RES0 Suzuki K Poulose <suzuki.poulose@arm.com> - 2017-01-04 19:50 +0100
    Re: [PATCH v3 1/9] arm64: cpufeature: treat unknown fields as RES0 Catalin Marinas <catalin.marinas@arm.com> - 2017-01-05 18:10 +0100
  [PATCH v3 5/9] arm64: cpufeature: Define helpers for sys_reg id Suzuki K Poulose <suzuki.poulose@arm.com> - 2017-01-04 19:50 +0100
    Re: [PATCH v3 5/9] arm64: cpufeature: Define helpers for sys_reg id Catalin Marinas <catalin.marinas@arm.com> - 2017-01-05 18:30 +0100
  [PATCH v3 7/9] arm64: cpufeature: Track user visible fields Suzuki K Poulose <suzuki.poulose@arm.com> - 2017-01-04 19:50 +0100
    Re: [PATCH v3 7/9] arm64: cpufeature: Track user visible fields Catalin Marinas <catalin.marinas@arm.com> - 2017-01-05 19:10 +0100
      Re: [PATCH v3 7/9] arm64: cpufeature: Track user visible fields Suzuki K Poulose <Suzuki.Poulose@arm.com> - 2017-01-06 12:20 +0100

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