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Groups > linux.kernel > #1548423
| From | "Li, Liang Z" <liang.z.li@intel.com> |
|---|---|
| Newsgroups | linux.kernel |
| Subject | RE: [PATCH RFC 0/4] 5-level EPT |
| Date | 2016-12-30 02:30 +0100 |
| Message-ID | <sTUb8-63e-9@gated-at.bofh.it> (permalink) |
| References | <sTFlL-4Oj-7@gated-at.bofh.it> <sTPEu-2W1-29@gated-at.bofh.it> |
| Organization | linux.* mail to news gateway |
> Subject: Re: [PATCH RFC 0/4] 5-level EPT > > On Thu, 29 Dec 2016 17:25:59 +0800, Liang Li said: > > x86-64 is currently limited physical address width to 46 bits, which > > can support 64 TiB of memory. Some vendors require to support more for > > some use case. Intel plans to extend the physical address width to > > 52 bits in some of the future products. > > Can you explain why this patchset mentions 52 bits in some places, and 57 in > others? Is it because there are currently in-process chipsets that will do 52, > but you want to future-proof it by extending it to 57 so future chipsets won't > need more work? Or is there some other reason? The 57-bits I referred in this patch set means the virtual address width which will be supported in the future CPU with 52-bits physical address width. 5 level EPT can support maximum 57-bits physical address width, as long as the future CPU use no more than 57-bits physical address width, no more work is needed. Thanks! Liang
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[PATCH RFC 0/4] 5-level EPT Liang Li <liang.z.li@intel.com> - 2016-12-29 10:40 +0100
[PATCH RFC 4/4] VMX: Expose the LA57 feature to VM Liang Li <liang.z.li@intel.com> - 2016-12-29 10:40 +0100
[PATCH RFC 2/4] KVM: MMU: Rename PT64_ROOT_LEVEL to PT64_ROOT_4LEVEL Liang Li <liang.z.li@intel.com> - 2016-12-29 10:40 +0100
[PATCH RFC 1/4] x86: Add the new CPUID and CR4 bits for 5 level page table Liang Li <liang.z.li@intel.com> - 2016-12-29 10:40 +0100
[PATCH RFC 3/4] KVM: MMU: Add 5 level EPT & Shadow page table support. Liang Li <liang.z.li@intel.com> - 2016-12-29 10:40 +0100
Re: [PATCH RFC 0/4] 5-level EPT Valdis.Kletnieks@vt.edu - 2016-12-29 21:40 +0100
RE: [PATCH RFC 0/4] 5-level EPT "Li, Liang Z" <liang.z.li@intel.com> - 2016-12-30 02:30 +0100
Re: [PATCH RFC 0/4] 5-level EPT Paolo Bonzini <pbonzini@redhat.com> - 2017-01-02 11:20 +0100
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