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[PATCH RFC 1/4] x86: Add the new CPUID and CR4 bits for 5 level page table

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Define the related bits for the 5 level page table, which supports
57 bits width virtual address space. This patch maybe included in
Kirill's patch set which enables 5 level page table for x86,
because 5 level EPT doesn't depend on 5 level page table, we put
it here for independence.

Signed-off-by: Liang Li <liang.z.li@intel.com>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: Kirill A. Shutemov <kirill.shutemov@linux.intel.com>
Cc: Dave Hansen <dave.hansen@linux.intel.com>
Cc: Xiao Guangrong <guangrong.xiao@linux.intel.com>
Cc: Paolo Bonzini <pbonzini@redhat.com>
Cc: "Radim Krčmář" <rkrcmar@redhat.com>
---
 arch/x86/include/asm/cpufeatures.h          | 1 +
 arch/x86/include/uapi/asm/processor-flags.h | 2 ++
 2 files changed, 3 insertions(+)

diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h
index eafee31..2cf4018 100644
--- a/arch/x86/include/asm/cpufeatures.h
+++ b/arch/x86/include/asm/cpufeatures.h
@@ -288,6 +288,7 @@
 #define X86_FEATURE_AVX512VBMI  (16*32+ 1) /* AVX512 Vector Bit Manipulation instructions*/
 #define X86_FEATURE_PKU		(16*32+ 3) /* Protection Keys for Userspace */
 #define X86_FEATURE_OSPKE	(16*32+ 4) /* OS Protection Keys Enable */
+#define X86_FEATURE_LA57	(16*32 + 16) /* 5-level page tables */
 #define X86_FEATURE_RDPID	(16*32+ 22) /* RDPID instruction */
 
 /* AMD-defined CPU features, CPUID level 0x80000007 (ebx), word 17 */
diff --git a/arch/x86/include/uapi/asm/processor-flags.h b/arch/x86/include/uapi/asm/processor-flags.h
index 567de50..185f3d1 100644
--- a/arch/x86/include/uapi/asm/processor-flags.h
+++ b/arch/x86/include/uapi/asm/processor-flags.h
@@ -104,6 +104,8 @@
 #define X86_CR4_OSFXSR		_BITUL(X86_CR4_OSFXSR_BIT)
 #define X86_CR4_OSXMMEXCPT_BIT	10 /* enable unmasked SSE exceptions */
 #define X86_CR4_OSXMMEXCPT	_BITUL(X86_CR4_OSXMMEXCPT_BIT)
+#define X86_CR4_LA57_BIT	12 /* enable 5-level page tables */
+#define X86_CR4_LA57		_BITUL(X86_CR4_LA57_BIT)
 #define X86_CR4_VMXE_BIT	13 /* enable VMX virtualization */
 #define X86_CR4_VMXE		_BITUL(X86_CR4_VMXE_BIT)
 #define X86_CR4_SMXE_BIT	14 /* enable safer mode (TXT) */
-- 
1.9.1

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[PATCH RFC 0/4] 5-level EPT Liang Li <liang.z.li@intel.com> - 2016-12-29 10:40 +0100
  [PATCH RFC 4/4] VMX: Expose the LA57 feature to VM Liang Li <liang.z.li@intel.com> - 2016-12-29 10:40 +0100
  [PATCH RFC 2/4] KVM: MMU: Rename PT64_ROOT_LEVEL to PT64_ROOT_4LEVEL Liang Li <liang.z.li@intel.com> - 2016-12-29 10:40 +0100
  [PATCH RFC 1/4] x86: Add the new CPUID and CR4 bits for 5 level page table Liang Li <liang.z.li@intel.com> - 2016-12-29 10:40 +0100
  [PATCH RFC 3/4] KVM: MMU: Add 5 level EPT & Shadow page table support. Liang Li <liang.z.li@intel.com> - 2016-12-29 10:40 +0100
  Re: [PATCH RFC 0/4] 5-level EPT Valdis.Kletnieks@vt.edu - 2016-12-29 21:40 +0100
    RE: [PATCH RFC 0/4] 5-level EPT "Li, Liang Z" <liang.z.li@intel.com> - 2016-12-30 02:30 +0100
  Re: [PATCH RFC 0/4] 5-level EPT Paolo Bonzini <pbonzini@redhat.com> - 2017-01-02 11:20 +0100

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