RE: [Patch v11 4/5] x86/cpufeature: enable RING3MWAIT for Knights Landing

From	"Andrejczuk, Grzegorz" <grzegorz.andrejczuk@intel.com>
Newsgroups	linux.kernel
Subject	RE: [Patch v11 4/5] x86/cpufeature: enable RING3MWAIT for Knights Landing
Date	2016-12-23 19:20 +0100
Message-ID	<sRCBH-1X2-9@gated-at.bofh.it> (permalink)
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On Thursday, December 22, 2016 3:21 PM Thomas Gleixner wrote:
> Changing types to match is the proper solution to all problems? You cannot
> just change types to make the compiler happy. You have to check what type
> is expected for it in the places which consume it, including compat mode.

HWCAP is u32 on x86 architecture, HWCAP2 on other architectures is uint.
I think I will be consistent with architecture and use u32 and bit OR operator.
It should be handled same way as ELF_HWCAP in user space and in 32 bits.
Please let me know if you agree to this solution. 

> What has the MSR to do with ELF_HWCAP2? ELF_HWCAP2 is a system global
> variable. The MSR is of course per hardware thread.

You are right - nothing. I can set HWCAP2 once for boot cpu.
To achieve that I need to distinguish boot cpu in probe_xeon_phi_r3mwait.
From looking around the kernel code I suspect it can be done like below:

if (c == &boot_cpu_data)
        ELF_HWCAP2 |= HWCAP2_RING3MWAIT;

If there's a better way, please let me know.  

> CPU bringup is serialized, i.e. init_intel() cannot run concurrently on
> different CPUs.

Thank you for your explanation, time and effort.
Merry Christmas,
Grzegorz

Thread

[PATCH v11 0/5] Enabling Ring 3 MONITOR/MWAIT feature for Knights Landing Grzegorz Andrejczuk <grzegorz.andrejczuk@intel.com> - 2016-12-20 14:50 +0100
  [PATCH v11 4/5] x86/cpufeature: enable RING3MWAIT for Knights Landing Grzegorz Andrejczuk <grzegorz.andrejczuk@intel.com> - 2016-12-20 14:50 +0100
    [Patch v11 4/5] x86/cpufeature: enable RING3MWAIT for Knights Landing Grzegorz Andrejczuk <grzegorz.andrejczuk@intel.com> - 2016-12-20 19:40 +0100
      Re: [Patch v11 4/5] x86/cpufeature: enable RING3MWAIT for Knights  Landing Thomas Gleixner <tglx@linutronix.de> - 2016-12-21 21:30 +0100
        RE: [Patch v11 4/5] x86/cpufeature: enable RING3MWAIT for Knights  Landing "Andrejczuk, Grzegorz" <grzegorz.andrejczuk@intel.com> - 2016-12-22 11:30 +0100
          RE: [Patch v11 4/5] x86/cpufeature: enable RING3MWAIT for Knights  Landing Thomas Gleixner <tglx@linutronix.de> - 2016-12-22 12:10 +0100
            RE: [Patch v11 4/5] x86/cpufeature: enable RING3MWAIT for Knights  Landing "Andrejczuk, Grzegorz" <grzegorz.andrejczuk@intel.com> - 2016-12-22 12:40 +0100
              RE: [Patch v11 4/5] x86/cpufeature: enable RING3MWAIT for Knights  Landing Thomas Gleixner <tglx@linutronix.de> - 2016-12-22 15:30 +0100
                RE: [Patch v11 4/5] x86/cpufeature: enable RING3MWAIT for Knights  Landing "Andrejczuk, Grzegorz" <grzegorz.andrejczuk@intel.com> - 2016-12-23 19:20 +0100
  [PATCH v11 2/5] x86/elf: add HWCAP2 to expose ring 3 MONITOR/MWAIT Grzegorz Andrejczuk <grzegorz.andrejczuk@intel.com> - 2016-12-20 14:50 +0100
  [PATCH v11 5/5] x86/cpufeature: enable RING3MWAIT for Knights Mill Grzegorz Andrejczuk <grzegorz.andrejczuk@intel.com> - 2016-12-20 15:00 +0100
  [PATCH v11 3/5] x86/cpufeature: add RING3MWAIT to CPU features Grzegorz Andrejczuk <grzegorz.andrejczuk@intel.com> - 2016-12-20 15:10 +0100
  [PATCH v11 1/5] x86/msr: add MSR_MISC_FEATURE_ENABLES and RING3MWAIT bit Grzegorz Andrejczuk <grzegorz.andrejczuk@intel.com> - 2016-12-20 15:20 +0100
    Re: [PATCH v11 1/5] x86/msr: add MSR_MISC_FEATURE_ENABLES and  RING3MWAIT bit Thomas Gleixner <tglx@linutronix.de> - 2016-12-21 21:30 +0100
      RE: [PATCH v11 1/5] x86/msr: add MSR_MISC_FEATURE_ENABLES and  RING3MWAIT bit "Andrejczuk, Grzegorz" <grzegorz.andrejczuk@intel.com> - 2016-12-22 10:20 +0100

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