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Re: [PATCH v11 1/5] x86/msr: add MSR_MISC_FEATURE_ENABLES and RING3MWAIT bit

From Thomas Gleixner <tglx@linutronix.de>
Newsgroups linux.kernel
Subject Re: [PATCH v11 1/5] x86/msr: add MSR_MISC_FEATURE_ENABLES and RING3MWAIT bit
Date 2016-12-21 21:30 +0100
Message-ID <sQVGq-85N-19@gated-at.bofh.it> (permalink)
References <sQsXL-6e4-7@gated-at.bofh.it> <sQtqO-6G9-19@gated-at.bofh.it>
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On Tue, 20 Dec 2016, Grzegorz Andrejczuk wrote:
> 
> diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h
> index 78f3760..55ffae0 100644
> --- a/arch/x86/include/asm/msr-index.h
> +++ b/arch/x86/include/asm/msr-index.h
> @@ -539,6 +539,12 @@
>  #define MSR_IA32_MISC_ENABLE_IP_PREF_DISABLE_BIT	39
>  #define MSR_IA32_MISC_ENABLE_IP_PREF_DISABLE		(1ULL << MSR_IA32_MISC_ENABLE_IP_PREF_DISABLE_BIT)
>  
> +/* MISC_FEATURE_ENABLES non-architectural features */
> +#define MSR_MISC_FEATURE_ENABLES		0x00000140
> +
> +#define MSR_MISC_FEATURE_ENABLES_RING3MWAIT_BIT		1
> +#define MSR_MISC_FEATURE_ENABLES_RING3MWAIT		(1ULL << MSR_MISC_FEATURE_ENABLES_RING3MWAIT_BIT)
> +

This last define is not used anywhere. I told you before, but addressing my
review comments completely is an unduly burden, or what?

Thanks,

	tglx

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[PATCH v11 0/5] Enabling Ring 3 MONITOR/MWAIT feature for Knights Landing Grzegorz Andrejczuk <grzegorz.andrejczuk@intel.com> - 2016-12-20 14:50 +0100
  [PATCH v11 4/5] x86/cpufeature: enable RING3MWAIT for Knights Landing Grzegorz Andrejczuk <grzegorz.andrejczuk@intel.com> - 2016-12-20 14:50 +0100
    [Patch v11 4/5] x86/cpufeature: enable RING3MWAIT for Knights Landing Grzegorz Andrejczuk <grzegorz.andrejczuk@intel.com> - 2016-12-20 19:40 +0100
      Re: [Patch v11 4/5] x86/cpufeature: enable RING3MWAIT for Knights  Landing Thomas Gleixner <tglx@linutronix.de> - 2016-12-21 21:30 +0100
        RE: [Patch v11 4/5] x86/cpufeature: enable RING3MWAIT for Knights  Landing "Andrejczuk, Grzegorz" <grzegorz.andrejczuk@intel.com> - 2016-12-22 11:30 +0100
          RE: [Patch v11 4/5] x86/cpufeature: enable RING3MWAIT for Knights  Landing Thomas Gleixner <tglx@linutronix.de> - 2016-12-22 12:10 +0100
            RE: [Patch v11 4/5] x86/cpufeature: enable RING3MWAIT for Knights  Landing "Andrejczuk, Grzegorz" <grzegorz.andrejczuk@intel.com> - 2016-12-22 12:40 +0100
              RE: [Patch v11 4/5] x86/cpufeature: enable RING3MWAIT for Knights  Landing Thomas Gleixner <tglx@linutronix.de> - 2016-12-22 15:30 +0100
                RE: [Patch v11 4/5] x86/cpufeature: enable RING3MWAIT for Knights  Landing "Andrejczuk, Grzegorz" <grzegorz.andrejczuk@intel.com> - 2016-12-23 19:20 +0100
  [PATCH v11 2/5] x86/elf: add HWCAP2 to expose ring 3 MONITOR/MWAIT Grzegorz Andrejczuk <grzegorz.andrejczuk@intel.com> - 2016-12-20 14:50 +0100
  [PATCH v11 5/5] x86/cpufeature: enable RING3MWAIT for Knights Mill Grzegorz Andrejczuk <grzegorz.andrejczuk@intel.com> - 2016-12-20 15:00 +0100
  [PATCH v11 3/5] x86/cpufeature: add RING3MWAIT to CPU features Grzegorz Andrejczuk <grzegorz.andrejczuk@intel.com> - 2016-12-20 15:10 +0100
  [PATCH v11 1/5] x86/msr: add MSR_MISC_FEATURE_ENABLES and RING3MWAIT bit Grzegorz Andrejczuk <grzegorz.andrejczuk@intel.com> - 2016-12-20 15:20 +0100
    Re: [PATCH v11 1/5] x86/msr: add MSR_MISC_FEATURE_ENABLES and  RING3MWAIT bit Thomas Gleixner <tglx@linutronix.de> - 2016-12-21 21:30 +0100
      RE: [PATCH v11 1/5] x86/msr: add MSR_MISC_FEATURE_ENABLES and  RING3MWAIT bit "Andrejczuk, Grzegorz" <grzegorz.andrejczuk@intel.com> - 2016-12-22 10:20 +0100

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