Groups | Search | Server Info | Keyboard shortcuts | Login | Register [http] [https] [nntp] [nntps]
Groups > linux.kernel > #1528585
| From | Tony Luck <tony.luck@gmail.com> |
|---|---|
| Newsgroups | linux.kernel |
| Subject | Re: [PATCH v2] x86/mce: Include the PPIN in machine check records when it is available |
| Date | 2016-11-23 17:50 +0100 |
| Message-ID | <sGIUa-7ig-37@gated-at.bofh.it> (permalink) |
| References | (1 earlier) <sEVsu-1L1-31@gated-at.bofh.it> <sGEdQ-4jn-15@gated-at.bofh.it> <sGFWi-5vy-5@gated-at.bofh.it> <sGFWi-5vy-35@gated-at.bofh.it> <sGHbI-6cs-19@gated-at.bofh.it> |
| Organization | linux.* mail to news gateway |
If the BIOS writes 10b, then PPIN is disabled and will remain so until the processor is reset. Bit 1 is a one way trip, it can be set by s/w, but not cleared again. All this is because of the huge stink last time Intel tried to add a serial number to CPUs a decade and a half ago. The lockout bit is so that this can be turned off in a way that you can be sure that it can't be turned on again. -Tony Sent from my iPhone > On Nov 23, 2016, at 06:05, Borislav Petkov <bp@suse.de> wrote: > >> On Wed, Nov 23, 2016 at 02:37:23PM +0100, Borislav Petkov wrote: >> You can't reenable it: >> >> "LockOut (R/WO) >> Set 1 to prevent further writes to MSR_PPIN_CTL. Writing 1 to >> MSR_PPINCTL[bit 0] is permitted only if MSR_PPIN_CTL[bit 1] is >> clear, Default is 0." > > Well, almost. > > "Enable_PPIN (R/W) > If 1, enables MSR_PPIN to be accessible using RDMSR. Once set, > attempt to write 1 to MSR_PPIN_CTL[bit 0] will cause #GP. > If 0, an attempt to read MSR_PPIN will cause #GP. Default is 0." > > Frankly, I don't get what the deal behind that locking out is. And it > says that BIOS should provide an opt-in so that agent can read the PPIN > and then that agent should *disable* it again by writing 01b to the CTL > MSR. > > But then the first paragraph above says that the write > MSR_PPIN_CTL[0]=1b will #GP because MSR_PPIN_CTL[1] will be 1 for the > agent to read out MSR_PPIN first. > > I guess we need to write a 00b first to disable PPIN and then write 01b > to lock it out. > > So AFAIU, the steps will be: > > * BIOS writes 10b > * agent reads MSR_PPIN > * agent writes 00b to disable MSR_PPIN > * agent writes 01b because bit 1 is clear now and it won't #GP. > > Meh... > > -- > Regards/Gruss, > Boris. > > SUSE Linux GmbH, GF: Felix Imendörffer, Jane Smithard, Graham Norton, HRB 21284 (AG Nürnberg) > --
Back to linux.kernel | Previous | Next — Previous in thread | Next in thread | Find similar | Unroll thread
[PATCH 2/2] mcelog: Print the PPIN in machine check records when it is available "Luck, Tony" <tony.luck@intel.com> - 2016-11-18 01:40 +0100
[PATCH 1/2] x86/mce: Include the PPIN in machine check records when it is available "Luck, Tony" <tony.luck@intel.com> - 2016-11-18 01:40 +0100
Re: [PATCH 1/2] x86/mce: Include the PPIN in machine check records when it is available Borislav Petkov <bp@suse.de> - 2016-11-18 14:10 +0100
Re: [PATCH 1/2] x86/mce: Include the PPIN in machine check records when it is available "Luck, Tony" <tony.luck@intel.com> - 2016-11-18 17:50 +0100
Re: [PATCH 1/2] x86/mce: Include the PPIN in machine check records when it is available Andi Kleen <andi@firstfloor.org> - 2016-11-18 18:10 +0100
Re: [PATCH 1/2] x86/mce: Include the PPIN in machine check records when it is available Borislav Petkov <bp@suse.de> - 2016-11-18 18:50 +0100
[PATCH v2] x86/mce: Include the PPIN in machine check records when it is available "Luck, Tony" <tony.luck@intel.com> - 2016-11-18 18:50 +0100
Re: [PATCH v2] x86/mce: Include the PPIN in machine check records when it is available Borislav Petkov <bp@suse.de> - 2016-11-23 12:50 +0100
Re: [PATCH v2] x86/mce: Include the PPIN in machine check records when it is available Henrique de Moraes Holschuh <hmh@hmh.eng.br> - 2016-11-23 14:40 +0100
Re: [PATCH v2] x86/mce: Include the PPIN in machine check records when it is available Borislav Petkov <bp@suse.de> - 2016-11-23 14:40 +0100
Re: [PATCH v2] x86/mce: Include the PPIN in machine check records when it is available Borislav Petkov <bp@suse.de> - 2016-11-23 16:00 +0100
Re: [PATCH v2] x86/mce: Include the PPIN in machine check records when it is available Tony Luck <tony.luck@gmail.com> - 2016-11-23 17:50 +0100
Re: [PATCH v2] x86/mce: Include the PPIN in machine check records when it is available Borislav Petkov <bp@suse.de> - 2016-11-23 18:00 +0100
Re: [PATCH v2] x86/mce: Include the PPIN in machine check records when it is available Henrique de Moraes Holschuh <hmh@hmh.eng.br> - 2016-11-23 18:30 +0100
Re: [PATCH v2] x86/mce: Include the PPIN in machine check records when it is available Tony Luck <tony.luck@gmail.com> - 2016-11-23 22:00 +0100
Re: [PATCH v2] x86/mce: Include the PPIN in machine check records when it is available Henrique de Moraes Holschuh <hmh@hmh.eng.br> - 2016-11-24 12:30 +0100
[tip:ras/core] x86/mce: Include the PPIN in MCE records when available tip-bot for Tony Luck <tipbot@zytor.com> - 2016-11-23 17:00 +0100
csiph-web