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Groups > linux.kernel > #1518403
| From | Joel Holdsworth <joel@airwebreathe.org.uk> |
|---|---|
| Newsgroups | linux.kernel |
| Subject | Re: [PATCH v8 3/3] fpga: Add support for Lattice iCE40 FPGAs |
| Date | 2016-11-09 19:40 +0100 |
| Message-ID | <sBFWW-2xe-35@gated-at.bofh.it> (permalink) |
| References | (3 earlier) <sAXjd-74X-49@gated-at.bofh.it> <sBd4C-lV-17@gated-at.bofh.it> <sBi4i-3IU-9@gated-at.bofh.it> <sBixk-3SR-47@gated-at.bofh.it> <sBFDA-2qo-27@gated-at.bofh.it> |
| Organization | linux.* mail to news gateway |
On 09/11/16 05:01, Marek Vasut wrote:
> On 11/08/2016 06:30 PM, Joel Holdsworth wrote:
>>>>> On the whole, I don't think the zero-length transfers are too
>>>>> egregiously bad, and all the alternatives seem worse to me.
>>>>
>>>> So why not turn the CS line into GPIO and just toggle the GPIO?
>>>
>>> Does that work with *all* SPI controllers?
>>>
>>
>> It does not - no. See my other email.
>
> And is that line an actual CS of that lattice chip or a generic input
> which almost works like CS?
>
I mean a generic output vs. a special CS output built into the SPI
master of the application processor. Take a look at how spi_set_cs(..)
works:
https://git.kernel.org/cgit/linux/kernel/git/torvalds/linux.git/tree/drivers/spi/spi.c?id=refs/tags/v4.9-rc4#n695
static void spi_set_cs(struct spi_device *spi, bool enable)
{
if (spi->mode & SPI_CS_HIGH)
enable = !enable;
if (gpio_is_valid(spi->cs_gpio))
gpio_set_value(spi->cs_gpio, !enable);
else if (spi->master->set_cs)
spi->master->set_cs(spi, !enable);
}
So on some SPI masters, spi->master->set_cs is handled separately from
normal GPIOs. Hence why I want to use this machinery, rather than doing
it with a GPIO.
Joel
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[PATCH v8 1/3] of: Add vendor prefix for Lattice Semiconductor Joel Holdsworth <joel@airwebreathe.org.uk> - 2016-11-07 04:00 +0100
[PATCH v8 3/3] fpga: Add support for Lattice iCE40 FPGAs Joel Holdsworth <joel@airwebreathe.org.uk> - 2016-11-07 04:00 +0100
Re: [PATCH v8 3/3] fpga: Add support for Lattice iCE40 FPGAs Moritz Fischer <moritz.fischer@ettus.com> - 2016-11-07 19:30 +0100
Re: [PATCH v8 3/3] fpga: Add support for Lattice iCE40 FPGAs Joel Holdsworth <joel@airwebreathe.org.uk> - 2016-11-07 20:10 +0100
Re: [PATCH v8 3/3] fpga: Add support for Lattice iCE40 FPGAs Moritz Fischer <moritz.fischer@ettus.com> - 2016-11-07 22:50 +0100
Re: [PATCH v8 3/3] fpga: Add support for Lattice iCE40 FPGAs Marek Vasut <marex@denx.de> - 2016-11-07 19:30 +0100
Re: [PATCH v8 3/3] fpga: Add support for Lattice iCE40 FPGAs Joel Holdsworth <joel@airwebreathe.org.uk> - 2016-11-07 20:00 +0100
Re: [PATCH v8 3/3] fpga: Add support for Lattice iCE40 FPGAs Marek Vasut <marex@denx.de> - 2016-11-08 12:50 +0100
Re: [PATCH v8 3/3] fpga: Add support for Lattice iCE40 FPGAs Moritz Fischer <moritz.fischer@ettus.com> - 2016-11-08 18:10 +0100
Re: [PATCH v8 3/3] fpga: Add support for Lattice iCE40 FPGAs Joel Holdsworth <joel@airwebreathe.org.uk> - 2016-11-08 18:40 +0100
Re: [PATCH v8 3/3] fpga: Add support for Lattice iCE40 FPGAs Marek Vasut <marex@denx.de> - 2016-11-09 19:20 +0100
Re: [PATCH v8 3/3] fpga: Add support for Lattice iCE40 FPGAs Joel Holdsworth <joel@airwebreathe.org.uk> - 2016-11-09 19:40 +0100
Re: [PATCH v8 3/3] fpga: Add support for Lattice iCE40 FPGAs Marek Vasut <marex@denx.de> - 2016-11-09 19:50 +0100
Re: [PATCH v8 3/3] fpga: Add support for Lattice iCE40 FPGAs Joel Holdsworth <joel@airwebreathe.org.uk> - 2016-11-09 20:00 +0100
Re: [PATCH v8 3/3] fpga: Add support for Lattice iCE40 FPGAs Marek Vasut <marex@denx.de> - 2016-11-10 18:00 +0100
Re: [PATCH v8 3/3] fpga: Add support for Lattice iCE40 FPGAs Joel Holdsworth <joel@airwebreathe.org.uk> - 2016-11-08 18:20 +0100
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