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Groups > linux.kernel > #1518333
| From | Matthias Brugger <matthias.bgg@gmail.com> |
|---|---|
| Newsgroups | linux.kernel |
| Subject | Re: [PATCH v15 4/4] arm: dts: mt2701: Use real clock for UARTs |
| Date | 2016-11-09 18:30 +0100 |
| Message-ID | <sBERc-1R9-27@gated-at.bofh.it> (permalink) |
| References | <szHq9-79q-7@gated-at.bofh.it> <szHq9-79q-13@gated-at.bofh.it> |
| Organization | linux.* mail to news gateway |
On 11/04/2016 08:43 AM, Erin Lo wrote:
> We used to use a fixed rate clock for the UARTs. Now that we have clock
> support we can associate the correct clocks to the UARTs and drop the
> 26MHz fixed rate UART clock.
>
> Signed-off-by: Erin Lo <erin.lo@mediatek.com>
Applied, thanks.
> ---
> arch/arm/boot/dts/mt2701.dtsi | 18 ++++++++----------
> 1 file changed, 8 insertions(+), 10 deletions(-)
>
> diff --git a/arch/arm/boot/dts/mt2701.dtsi b/arch/arm/boot/dts/mt2701.dtsi
> index c9a8dbf..7eab6f4 100644
> --- a/arch/arm/boot/dts/mt2701.dtsi
> +++ b/arch/arm/boot/dts/mt2701.dtsi
> @@ -73,12 +73,6 @@
> #clock-cells = <0>;
> };
>
> - uart_clk: dummy26m {
> - compatible = "fixed-clock";
> - clock-frequency = <26000000>;
> - #clock-cells = <0>;
> - };
> -
> clk26m: oscillator@0 {
> compatible = "fixed-clock";
> #clock-cells = <0>;
> @@ -186,7 +180,8 @@
> "mediatek,mt6577-uart";
> reg = <0 0x11002000 0 0x400>;
> interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_LOW>;
> - clocks = <&uart_clk>;
> + clocks = <&pericfg CLK_PERI_UART0_SEL>, <&pericfg CLK_PERI_UART0>;
> + clock-names = "baud", "bus";
> status = "disabled";
> };
>
> @@ -195,7 +190,8 @@
> "mediatek,mt6577-uart";
> reg = <0 0x11003000 0 0x400>;
> interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_LOW>;
> - clocks = <&uart_clk>;
> + clocks = <&pericfg CLK_PERI_UART1_SEL>, <&pericfg CLK_PERI_UART1>;
> + clock-names = "baud", "bus";
> status = "disabled";
> };
>
> @@ -204,7 +200,8 @@
> "mediatek,mt6577-uart";
> reg = <0 0x11004000 0 0x400>;
> interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_LOW>;
> - clocks = <&uart_clk>;
> + clocks = <&pericfg CLK_PERI_UART2_SEL>, <&pericfg CLK_PERI_UART2>;
> + clock-names = "baud", "bus";
> status = "disabled";
> };
>
> @@ -213,7 +210,8 @@
> "mediatek,mt6577-uart";
> reg = <0 0x11005000 0 0x400>;
> interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_LOW>;
> - clocks = <&uart_clk>;
> + clocks = <&pericfg CLK_PERI_UART3_SEL>, <&pericfg CLK_PERI_UART3>;
> + clock-names = "baud", "bus";
> status = "disabled";
> };
> };
>
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[PATCH v15 0/4] Add clock support for Mediatek MT2701 Erin Lo <erin.lo@mediatek.com> - 2016-11-04 08:50 +0100
[PATCH v15 2/4] reset: mediatek: Add MT2701 reset driver Erin Lo <erin.lo@mediatek.com> - 2016-11-04 08:50 +0100
Re: [PATCH v15 2/4] reset: mediatek: Add MT2701 reset driver Stephen Boyd <sboyd@codeaurora.org> - 2016-11-09 01:10 +0100
[PATCH v15 4/4] arm: dts: mt2701: Use real clock for UARTs Erin Lo <erin.lo@mediatek.com> - 2016-11-04 08:50 +0100
Re: [PATCH v15 4/4] arm: dts: mt2701: Use real clock for UARTs Matthias Brugger <matthias.bgg@gmail.com> - 2016-11-09 18:30 +0100
[PATCH v15 3/4] arm: dts: mt2701: Add clock controller device nodes Erin Lo <erin.lo@mediatek.com> - 2016-11-04 08:50 +0100
Re: [PATCH v15 1/4] clk: mediatek: Add MT2701 clock support Stephen Boyd <sboyd@codeaurora.org> - 2016-11-09 01:10 +0100
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