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Groups > linux.kernel > #1469630
| From | Peter Zijlstra <peterz@infradead.org> |
|---|---|
| Newsgroups | linux.kernel |
| Subject | Re: [PATCH v2] perf/x86/amd: Make HW_CACHE_REFERENCES and HW_CACHE_MISSES measure L2 |
| Date | 2016-08-24 20:30 +0200 |
| Message-ID | <s9L61-62m-13@gated-at.bofh.it> (permalink) |
| References | <s9Gg1-2I8-13@gated-at.bofh.it> <s9HON-3F4-7@gated-at.bofh.it> |
| Organization | linux.* mail to news gateway |
On Wed, Aug 24, 2016 at 04:55:14PM +0200, Borislav Petkov wrote: > On Wed, Aug 24, 2016 at 02:12:08PM +0100, Matt Fleming wrote: > > While the Intel PMU monitors the LLC when perf enables the > > HW_CACHE_REFERENCES and HW_CACHE_MISSES events, these events monitor > > L1 instruction cache fetches (0x0080) and instruction cache misses > > (0x0081) on the AMD PMU. > > > > This is extremely confusing when monitoring the same workload across > > Intel and AMD machines, since parameters like, > > > > $ perf stat -e cache-references,cache-misses > > > > measure completely different things. > > > > Instead, make the AMD PMU measure instruction/data cache and TLB fill > > requests to the L2 and instruction/data cache and TLB misses in the L2 > > when HW_CACHE_REFERENCES and HW_CACHE_MISSES are enabled, > > respectively. That way the events measure unified caches on both > > platforms. > > I'm still not really sure about this: we can't really compare L3 to L2 > access patterns - it is almost as comparing apples to oranges. Can we > use the Intel L2 events instead? They're not meant to be comparable between machines. I wouldn't even compare the LLC numbers between two different Intel parts. These events are meant to profile a workload on the machine you run them on. Big cache-miss/ref ratios indicate you loose performance because of the memory subsystem and or data structure layout. And afaict AMD parts, even those that have L3, cannot provide L3 numbers on a per task basis, so these L2 numbers are the best we have.
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[PATCH v2] perf/x86/amd: Make HW_CACHE_REFERENCES and HW_CACHE_MISSES measure L2 Matt Fleming <matt@codeblueprint.co.uk> - 2016-08-24 15:20 +0200
Re: [PATCH v2] perf/x86/amd: Make HW_CACHE_REFERENCES and HW_CACHE_MISSES measure L2 Borislav Petkov <bp@alien8.de> - 2016-08-24 17:00 +0200
Re: [PATCH v2] perf/x86/amd: Make HW_CACHE_REFERENCES and HW_CACHE_MISSES measure L2 Peter Zijlstra <peterz@infradead.org> - 2016-08-24 20:30 +0200
Re: [PATCH v2] perf/x86/amd: Make HW_CACHE_REFERENCES and HW_CACHE_MISSES measure L2 Borislav Petkov <bp@alien8.de> - 2016-08-25 06:40 +0200
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