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Groups > linux.kernel > #1467472
| From | Chanwoo Choi <cw00.choi@samsung.com> |
|---|---|
| Newsgroups | linux.kernel |
| Subject | [PATCH 1/2] dt-bindings: Add the clock id for CMU_CDREX (DRAM Express Controller) |
| Date | 2016-08-22 10:50 +0200 |
| Message-ID | <s8T5D-3Zg-13@gated-at.bofh.it> (permalink) |
| References | <s8T5D-3Zg-7@gated-at.bofh.it> |
| Organization | linux.* mail to news gateway |
This patch adds the new clock id for CMU_CDRES (DRAM Express Controller) geneates the clocks for DRAM and NoC (Network on Chip) bus clock. Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com> --- include/dt-bindings/clock/exynos5420.h | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-) diff --git a/include/dt-bindings/clock/exynos5420.h b/include/dt-bindings/clock/exynos5420.h index 17ab8394bec7..6fd21c291416 100644 --- a/include/dt-bindings/clock/exynos5420.h +++ b/include/dt-bindings/clock/exynos5420.h @@ -214,6 +214,9 @@ #define CLK_MOUT_SW_ACLK400 651 #define CLK_MOUT_USER_ACLK300_GSCL 652 #define CLK_MOUT_SW_ACLK300_GSCL 653 +#define CLK_MOUT_MCLK_CDREX 654 +#define CLK_MOUT_BPLL 655 +#define CLK_MOUT_MX_MSPLL_CCORE 656 /* divider clocks */ #define CLK_DOUT_PIXEL 768 @@ -239,8 +242,14 @@ #define CLK_DOUT_ACLK300_DISP1 788 #define CLK_DOUT_ACLK300_GSCL 789 #define CLK_DOUT_ACLK400_DISP1 790 +#define CLK_DOUT_PCLK_CDREX 791 +#define CLK_DOUT_SCLK_CDREX 792 +#define CLK_DOUT_ACLK_CDREX1 793 +#define CLK_DOUT_CCLK_DREX0 794 +#define CLK_DOUT_CLK2X_PHY0 795 +#define CLK_DOUT_PCLK_CORE_MEM 796 /* must be greater than maximal clock id */ -#define CLK_NR_CLKS 791 +#define CLK_NR_CLKS 797 #endif /* _DT_BINDINGS_CLOCK_EXYNOS_5420_H */ -- 1.9.1
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[PATCH 0/2] clk: samsung: exynos5420: Add clocks for CMU_CDREX domain Chanwoo Choi <cw00.choi@samsung.com> - 2016-08-22 10:50 +0200 [PATCH 1/2] dt-bindings: Add the clock id for CMU_CDREX (DRAM Express Controller) Chanwoo Choi <cw00.choi@samsung.com> - 2016-08-22 10:50 +0200 [PATCH 2/2] clk: samsung: exynos5420: Add clocks for CMU_CDREX domain Chanwoo Choi <cw00.choi@samsung.com> - 2016-08-22 10:50 +0200 Re: [PATCH 0/2] clk: samsung: exynos5420: Add clocks for CMU_CDREX domain Chanwoo Choi <cw00.choi@samsung.com> - 2016-08-22 14:10 +0200
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