Re: [PATCH] perf/x86/amd: Make HW_CACHE_REFERENCES and HW_CACHE_MISSES measure L2

From	Peter Zijlstra <peterz@infradead.org>
Newsgroups	linux.kernel
Subject	Re: [PATCH] perf/x86/amd: Make HW_CACHE_REFERENCES and HW_CACHE_MISSES measure L2
Date	2016-08-19 17:20 +0200
Message-ID	<s7TKq-7i3-5@gated-at.bofh.it> (permalink)
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On Fri, Aug 19, 2016 at 04:44:53PM +0200, Borislav Petkov wrote:
> On Fri, Aug 19, 2016 at 03:34:22PM +0200, Peter Zijlstra wrote:
> > Can't those events are NB events and cannot be used on per CPU counters.
> 
> It fugures, considering L3 is part of the NB on AMD.
> 
> So the Intel ones are special in the sense that they can be used on per
> CPU counters even though they're not really per-CPU?

Intel has L3 (and L2,1) request and miss events per logical CPU. The CPU
still issues the load/store that causes the request and miss and thus
can be accounted to the program under execution.

Intel also has a bunch of L3 events at the uncore of course.

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[PATCH] perf/x86/amd: Make HW_CACHE_REFERENCES and HW_CACHE_MISSES measure L2 Matt Fleming <matt@codeblueprint.co.uk> - 2016-08-11 17:30 +0200
  Re: [PATCH] perf/x86/amd: Make HW_CACHE_REFERENCES and  HW_CACHE_MISSES measure L2 Borislav Petkov <bp@alien8.de> - 2016-08-11 18:50 +0200
    Re: [PATCH] perf/x86/amd: Make HW_CACHE_REFERENCES and  HW_CACHE_MISSES measure L2 Matt Fleming <matt@codeblueprint.co.uk> - 2016-08-15 17:20 +0200
      Re: [PATCH] perf/x86/amd: Make HW_CACHE_REFERENCES and  HW_CACHE_MISSES measure L2 Borislav Petkov <bp@alien8.de> - 2016-08-19 04:00 +0200
        Re: [PATCH] perf/x86/amd: Make HW_CACHE_REFERENCES and  HW_CACHE_MISSES measure L2 Peter Zijlstra <peterz@infradead.org> - 2016-08-19 15:40 +0200
          Re: [PATCH] perf/x86/amd: Make HW_CACHE_REFERENCES and  HW_CACHE_MISSES measure L2 Borislav Petkov <bp@alien8.de> - 2016-08-19 16:50 +0200
            Re: [PATCH] perf/x86/amd: Make HW_CACHE_REFERENCES and  HW_CACHE_MISSES measure L2 Peter Zijlstra <peterz@infradead.org> - 2016-08-19 17:20 +0200

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