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Groups > linux.kernel > #1466428
| From | Peter Zijlstra <peterz@infradead.org> |
|---|---|
| Newsgroups | linux.kernel |
| Subject | Re: [PATCH] perf/x86/amd: Make HW_CACHE_REFERENCES and HW_CACHE_MISSES measure L2 |
| Date | 2016-08-19 15:40 +0200 |
| Message-ID | <s7SbE-6dI-61@gated-at.bofh.it> (permalink) |
| References | <s505H-5ym-7@gated-at.bofh.it> <s51l7-6jV-23@gated-at.bofh.it> <s6rQd-7ef-1@gated-at.bofh.it> <s7Hge-7z4-23@gated-at.bofh.it> |
| Organization | linux.* mail to news gateway |
On Thu, Aug 18, 2016 at 06:25:22PM +0200, Borislav Petkov wrote: > > > I could try to find better/more fitting event selectors on AMD... > > > > If you've got any other suggestions, I'm all ears. > > So there are no LLC events on AMD in the sense that there are no > event selectors which always mean last-level cache and select those > automagically, no matter whether the LLC is the L2, L3 and so on, > depending on the part. > > If we have to be correct on AMD, we'd have to check whether the part has > an L3 and then choose the L3 events, say, something like > > "EventSelect 4E1h L3 Cache Misses" and "EventSelect 4E2h L3 Fills caused > by L2 Evictions" Can't those events are NB events and cannot be used on per CPU counters. The 7D,7E L2 events are the best that are available on AMD afaict.
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[PATCH] perf/x86/amd: Make HW_CACHE_REFERENCES and HW_CACHE_MISSES measure L2 Matt Fleming <matt@codeblueprint.co.uk> - 2016-08-11 17:30 +0200
Re: [PATCH] perf/x86/amd: Make HW_CACHE_REFERENCES and HW_CACHE_MISSES measure L2 Borislav Petkov <bp@alien8.de> - 2016-08-11 18:50 +0200
Re: [PATCH] perf/x86/amd: Make HW_CACHE_REFERENCES and HW_CACHE_MISSES measure L2 Matt Fleming <matt@codeblueprint.co.uk> - 2016-08-15 17:20 +0200
Re: [PATCH] perf/x86/amd: Make HW_CACHE_REFERENCES and HW_CACHE_MISSES measure L2 Borislav Petkov <bp@alien8.de> - 2016-08-19 04:00 +0200
Re: [PATCH] perf/x86/amd: Make HW_CACHE_REFERENCES and HW_CACHE_MISSES measure L2 Peter Zijlstra <peterz@infradead.org> - 2016-08-19 15:40 +0200
Re: [PATCH] perf/x86/amd: Make HW_CACHE_REFERENCES and HW_CACHE_MISSES measure L2 Borislav Petkov <bp@alien8.de> - 2016-08-19 16:50 +0200
Re: [PATCH] perf/x86/amd: Make HW_CACHE_REFERENCES and HW_CACHE_MISSES measure L2 Peter Zijlstra <peterz@infradead.org> - 2016-08-19 17:20 +0200
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