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Groups > linux.kernel > #1400403
| From | Brian Norris <briannorris@chromium.org> |
|---|---|
| Newsgroups | linux.kernel |
| Subject | [PATCH 4/4] phy: rockchip-emmc: reindent the register definitions |
| Date | 2016-05-13 00:50 +0200 |
| Message-ID | <ry7AC-77L-15@gated-at.bofh.it> (permalink) |
| References | <ry7AB-77L-3@gated-at.bofh.it> |
| Organization | linux.* mail to news gateway |
Some of the spacing was wrong (spaces instead of tabs), and due to longer entries added later, the columns weren't aligned. Let's get everything consistent. Signed-off-by: Brian Norris <briannorris@chromium.org> --- drivers/phy/phy-rockchip-emmc.c | 76 ++++++++++++++++++++--------------------- 1 file changed, 38 insertions(+), 38 deletions(-) diff --git a/drivers/phy/phy-rockchip-emmc.c b/drivers/phy/phy-rockchip-emmc.c index f94d3a6587ed..c27ca2b39dfe 100644 --- a/drivers/phy/phy-rockchip-emmc.c +++ b/drivers/phy/phy-rockchip-emmc.c @@ -31,44 +31,44 @@ ((val) << (shift) | (mask) << ((shift) + 16)) /* Register definition */ -#define GRF_EMMCPHY_CON0 0x0 -#define GRF_EMMCPHY_CON1 0x4 -#define GRF_EMMCPHY_CON2 0x8 -#define GRF_EMMCPHY_CON3 0xc -#define GRF_EMMCPHY_CON4 0x10 -#define GRF_EMMCPHY_CON5 0x14 -#define GRF_EMMCPHY_CON6 0x18 -#define GRF_EMMCPHY_STATUS 0x20 - -#define PHYCTRL_PDB_MASK 0x1 -#define PHYCTRL_PDB_SHIFT 0x0 -#define PHYCTRL_PDB_PWR_ON 0x1 -#define PHYCTRL_PDB_PWR_OFF 0x0 -#define PHYCTRL_ENDLL_MASK 0x1 -#define PHYCTRL_ENDLL_SHIFT 0x1 -#define PHYCTRL_ENDLL_ENABLE 0x1 -#define PHYCTRL_ENDLL_DISABLE 0x0 -#define PHYCTRL_CALDONE_MASK 0x1 -#define PHYCTRL_CALDONE_SHIFT 0x6 -#define PHYCTRL_CALDONE_DONE 0x1 -#define PHYCTRL_CALDONE_GOING 0x0 -#define PHYCTRL_DLLRDY_MASK 0x1 -#define PHYCTRL_DLLRDY_SHIFT 0x5 -#define PHYCTRL_DLLRDY_DONE 0x1 -#define PHYCTRL_DLLRDY_GOING 0x0 -#define PHYCTRL_FREQSEL_200M 0x0 -#define PHYCTRL_FREQSEL_50M 0x1 -#define PHYCTRL_FREQSEL_100M 0x2 -#define PHYCTRL_FREQSEL_150M 0x3 -#define PHYCTRL_FREQSEL_MASK 0x3 -#define PHYCTRL_FREQSEL_SHIFT 0xc -#define PHYCTRL_DR_MASK 0x7 -#define PHYCTRL_DR_SHIFT 0x4 -#define PHYCTRL_DR_50OHM 0x0 -#define PHYCTRL_DR_33OHM 0x1 -#define PHYCTRL_DR_66OHM 0x2 -#define PHYCTRL_DR_100OHM 0x3 -#define PHYCTRL_DR_40OHM 0x4 +#define GRF_EMMCPHY_CON0 0x0 +#define GRF_EMMCPHY_CON1 0x4 +#define GRF_EMMCPHY_CON2 0x8 +#define GRF_EMMCPHY_CON3 0xc +#define GRF_EMMCPHY_CON4 0x10 +#define GRF_EMMCPHY_CON5 0x14 +#define GRF_EMMCPHY_CON6 0x18 +#define GRF_EMMCPHY_STATUS 0x20 + +#define PHYCTRL_PDB_MASK 0x1 +#define PHYCTRL_PDB_SHIFT 0x0 +#define PHYCTRL_PDB_PWR_ON 0x1 +#define PHYCTRL_PDB_PWR_OFF 0x0 +#define PHYCTRL_ENDLL_MASK 0x1 +#define PHYCTRL_ENDLL_SHIFT 0x1 +#define PHYCTRL_ENDLL_ENABLE 0x1 +#define PHYCTRL_ENDLL_DISABLE 0x0 +#define PHYCTRL_CALDONE_MASK 0x1 +#define PHYCTRL_CALDONE_SHIFT 0x6 +#define PHYCTRL_CALDONE_DONE 0x1 +#define PHYCTRL_CALDONE_GOING 0x0 +#define PHYCTRL_DLLRDY_MASK 0x1 +#define PHYCTRL_DLLRDY_SHIFT 0x5 +#define PHYCTRL_DLLRDY_DONE 0x1 +#define PHYCTRL_DLLRDY_GOING 0x0 +#define PHYCTRL_FREQSEL_200M 0x0 +#define PHYCTRL_FREQSEL_50M 0x1 +#define PHYCTRL_FREQSEL_100M 0x2 +#define PHYCTRL_FREQSEL_150M 0x3 +#define PHYCTRL_FREQSEL_MASK 0x3 +#define PHYCTRL_FREQSEL_SHIFT 0xc +#define PHYCTRL_DR_MASK 0x7 +#define PHYCTRL_DR_SHIFT 0x4 +#define PHYCTRL_DR_50OHM 0x0 +#define PHYCTRL_DR_33OHM 0x1 +#define PHYCTRL_DR_66OHM 0x2 +#define PHYCTRL_DR_100OHM 0x3 +#define PHYCTRL_DR_40OHM 0x4 #define PHYCTRL_OTAPDLYENA 0x1 #define PHYCTRL_OTAPDLYENA_MASK 0x1 #define PHYCTRL_OTAPDLYENA_SHIFT 0xb -- 2.8.0.rc3.226.g39d4020
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[PATCH 1/4] phy: rockchip-emmc: give DLL some extra time to be ready Brian Norris <briannorris@chromium.org> - 2016-05-13 00:50 +0200
[PATCH 3/4] phy: rockchip-emmc: configure default output tap delay Brian Norris <briannorris@chromium.org> - 2016-05-13 00:50 +0200
Re: [PATCH 3/4] phy: rockchip-emmc: configure default output tap delay Doug Anderson <dianders@chromium.org> - 2016-05-14 00:30 +0200
Re: [PATCH 3/4] phy: rockchip-emmc: configure default output tap delay Shawn Lin <shawn.lin@rock-chips.com> - 2016-05-16 06:20 +0200
Re: [PATCH 3/4] phy: rockchip-emmc: configure default output tap delay Doug Anderson <dianders@chromium.org> - 2016-05-16 17:20 +0200
[PATCH 2/4] phy: rockchip-emmc: configure frequency range and drive impedance Brian Norris <briannorris@chromium.org> - 2016-05-13 00:50 +0200
Re: [PATCH 2/4] phy: rockchip-emmc: configure frequency range and drive impedance Shawn Lin <shawn.lin@rock-chips.com> - 2016-05-13 03:10 +0200
Re: [PATCH 2/4] phy: rockchip-emmc: configure frequency range and drive impedance Doug Anderson <dianders@chromium.org> - 2016-05-13 20:50 +0200
Re: [PATCH 2/4] phy: rockchip-emmc: configure frequency range and drive impedance Brian Norris <briannorris@chromium.org> - 2016-05-13 23:10 +0200
Re: [PATCH 2/4] phy: rockchip-emmc: configure frequency range and drive impedance Doug Anderson <dianders@chromium.org> - 2016-05-24 07:00 +0200
[PATCH v2 2/4] phy: rockchip-emmc: configure frequency range and drive impedance Brian Norris <briannorris@chromium.org> - 2016-05-13 23:10 +0200
Re: [PATCH v2 2/4] phy: rockchip-emmc: configure frequency range and drive impedance Doug Anderson <dianders@chromium.org> - 2016-05-14 00:10 +0200
[PATCH 4/4] phy: rockchip-emmc: reindent the register definitions Brian Norris <briannorris@chromium.org> - 2016-05-13 00:50 +0200
Re: [PATCH 4/4] phy: rockchip-emmc: reindent the register definitions Doug Anderson <dianders@chromium.org> - 2016-05-14 00:30 +0200
Re: [PATCH 1/4] phy: rockchip-emmc: give DLL some extra time to be ready Doug Anderson <dianders@chromium.org> - 2016-05-14 00:10 +0200
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