Groups | Search | Server Info | Keyboard shortcuts | Login | Register [http] [https] [nntp] [nntps]
Groups > linux.kernel > #1396452
| From | Borislav Petkov <bp@alien8.de> |
|---|---|
| Newsgroups | linux.kernel |
| Subject | [PATCH] x86/cpu: Correct small issues in P4 erratum 037 code |
| Date | 2016-05-08 21:00 +0200 |
| Message-ID | <rwC5P-3Ij-1@gated-at.bofh.it> (permalink) |
| Organization | linux.* mail to news gateway |
From: Borislav Petkov <bp@suse.de>
Remove the linebreak in the conditional and s/errata/erratum/ as the
singular is "erratum".
No functionality change.
Signed-off-by: Borislav Petkov <bp@suse.de>
---
arch/x86/kernel/cpu/intel.c | 7 +++----
1 file changed, 3 insertions(+), 4 deletions(-)
diff --git a/arch/x86/kernel/cpu/intel.c b/arch/x86/kernel/cpu/intel.c
index fcc0996afc9f..df9b912ff0fa 100644
--- a/arch/x86/kernel/cpu/intel.c
+++ b/arch/x86/kernel/cpu/intel.c
@@ -263,15 +263,14 @@ static void intel_workarounds(struct cpuinfo_x86 *c)
}
/*
- * P4 Xeon errata 037 workaround.
+ * P4 Xeon erratum 037 workaround.
* Hardware prefetcher may cause stale data to be loaded into the cache.
*/
if ((c->x86 == 15) && (c->x86_model == 1) && (c->x86_mask == 1)) {
if (msr_set_bit(MSR_IA32_MISC_ENABLE,
- MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE_BIT)
- > 0) {
+ MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE_BIT) > 0) {
pr_info("CPU: C0 stepping P4 Xeon detected.\n");
- pr_info("CPU: Disabling hardware prefetching (Errata 037)\n");
+ pr_info("CPU: Disabling hardware prefetching (Erratum 037)\n");
}
}
--
2.7.3
Back to linux.kernel | Previous | Next — Next in thread | Find similar | Unroll thread
[PATCH] x86/cpu: Correct small issues in P4 erratum 037 code Borislav Petkov <bp@alien8.de> - 2016-05-08 21:00 +0200 [tip:x86/cpu] x86/cpu: Correct comments and messages in P4 erratum 037 handling code tip-bot for Borislav Petkov <tipbot@zytor.com> - 2016-05-10 10:50 +0200
csiph-web