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[PATCH V4 04/18] coresight: tmc: clearly define number of transfers per burst

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This patch makes the name of the define reflect the amount of
data tranfers per burst, in this case 16.

Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
Reviewed-by: Suzuki K Poulose <suzuki.poulose@arm.com>
---
 drivers/hwtracing/coresight/coresight-tmc.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/hwtracing/coresight/coresight-tmc.c b/drivers/hwtracing/coresight/coresight-tmc.c
index d211aeec49f8..8751d53fa078 100644
--- a/drivers/hwtracing/coresight/coresight-tmc.c
+++ b/drivers/hwtracing/coresight/coresight-tmc.c
@@ -67,7 +67,7 @@
 #define TMC_AXICTL_PROT_CTL_B0	BIT(0)
 #define TMC_AXICTL_PROT_CTL_B1	BIT(1)
 #define TMC_AXICTL_SCT_GAT_MODE	BIT(7)
-#define TMC_AXICTL_WR_BURST_LEN 0xF00
+#define TMC_AXICTL_WR_BURST_16	0xF00
 /* TMC_FFCR - 0x304 */
 #define TMC_FFCR_EN_FMT		BIT(0)
 #define TMC_FFCR_EN_TI		BIT(1)
@@ -211,7 +211,7 @@ static void tmc_etr_enable_hw(struct tmc_drvdata *drvdata)
 	writel_relaxed(TMC_MODE_CIRCULAR_BUFFER, drvdata->base + TMC_MODE);
 
 	axictl = readl_relaxed(drvdata->base + TMC_AXICTL);
-	axictl |= TMC_AXICTL_WR_BURST_LEN;
+	axictl |= TMC_AXICTL_WR_BURST_16;
 	writel_relaxed(axictl, drvdata->base + TMC_AXICTL);
 	axictl &= ~TMC_AXICTL_SCT_GAT_MODE;
 	writel_relaxed(axictl, drvdata->base + TMC_AXICTL);
-- 
2.5.0

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[PATCH V4 00/18] coresight: tmc: make driver usable by Perf Mathieu Poirier <mathieu.poirier@linaro.org> - 2016-04-27 00:20 +0200
  [PATCH V4 09/18] coresight: tmc: allocating memory when needed Mathieu Poirier <mathieu.poirier@linaro.org> - 2016-04-27 00:20 +0200
  [PATCH V4 14/18] coresight: tmc: keep track of memory width Mathieu Poirier <mathieu.poirier@linaro.org> - 2016-04-27 00:20 +0200
  [PATCH V4 15/18] coresight: moving struct cs_buffers to header file Mathieu Poirier <mathieu.poirier@linaro.org> - 2016-04-27 00:20 +0200
  [PATCH V4 04/18] coresight: tmc: clearly define number of transfers per burst Mathieu Poirier <mathieu.poirier@linaro.org> - 2016-04-27 00:20 +0200
  [PATCH V4 16/18] coresight: tmc: implementing TMC-ETF AUX space API Mathieu Poirier <mathieu.poirier@linaro.org> - 2016-04-27 00:20 +0200
    Re: [PATCH V4 16/18] coresight: tmc: implementing TMC-ETF AUX space  API Suzuki K Poulose <Suzuki.Poulose@arm.com> - 2016-04-27 13:30 +0200
      Re: [PATCH V4 16/18] coresight: tmc: implementing TMC-ETF AUX space  API Suzuki K Poulose <Suzuki.Poulose@arm.com> - 2016-04-27 19:30 +0200
      Re: [PATCH V4 16/18] coresight: tmc: implementing TMC-ETF AUX space API Mathieu Poirier <mathieu.poirier@linaro.org> - 2016-04-27 19:30 +0200
  [PATCH V4 11/18] coresight: tmc: adding mode of operation for link/sinks Mathieu Poirier <mathieu.poirier@linaro.org> - 2016-04-27 00:20 +0200
    Re: [PATCH V4 11/18] coresight: tmc: adding mode of operation for  link/sinks Suzuki K Poulose <Suzuki.Poulose@arm.com> - 2016-04-27 11:10 +0200
  [PATCH V4 02/18] coresight: tmc: waiting for TMCReady bit before programming Mathieu Poirier <mathieu.poirier@linaro.org> - 2016-04-27 00:20 +0200
  [PATCH V4 10/18] coresight: tmc: getting rid of multiple read access Mathieu Poirier <mathieu.poirier@linaro.org> - 2016-04-27 00:20 +0200
    Re: [PATCH V4 10/18] coresight: tmc: getting rid of multiple read  access Suzuki K Poulose <Suzuki.Poulose@arm.com> - 2016-04-27 11:00 +0200
  [PATCH V4 05/18] coresight: tmc: introducing new header file Mathieu Poirier <mathieu.poirier@linaro.org> - 2016-04-27 00:20 +0200
  [PATCH V4 08/18] coresight: tmc: making prepare/unprepare functions generic Mathieu Poirier <mathieu.poirier@linaro.org> - 2016-04-27 00:20 +0200
  [PATCH V4 18/18] coresight: configuring ETF in FIFO mode when acting as link Mathieu Poirier <mathieu.poirier@linaro.org> - 2016-04-27 00:20 +0200
  [PATCH V4 06/18] coresight: tmc: cleaning up header file Mathieu Poirier <mathieu.poirier@linaro.org> - 2016-04-27 00:20 +0200

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