Re: [PATCH 2/2 v5] irqchip/Layerscape: Add SCFG MSI controller support

From	Marc Zyngier <marc.zyngier@arm.com>
Newsgroups	linux.kernel
Subject	Re: [PATCH 2/2 v5] irqchip/Layerscape: Add SCFG MSI controller support
Date	2016-04-22 09:50 +0200
Message-ID	<rqE0G-6O2-19@gated-at.bofh.it> (permalink)
References	<ra07g-1aG-11@gated-at.bofh.it> <ra07g-1aG-13@gated-at.bofh.it> <ra07g-1aG-9@gated-at.bofh.it> <rqBYR-5ad-3@gated-at.bofh.it>
Organization	ARM Ltd

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On 22/04/16 06:33, Leo Li wrote:
> On Mon, Mar 7, 2016 at 3:50 AM, Marc Zyngier <marc.zyngier@arm.com> wrote:
>> On Mon, 7 Mar 2016 11:36:22 +0800
>> Minghuan Lian <Minghuan.Lian@nxp.com> wrote:
>>
>>> Some kind of NXP Layerscape SoC provides a MSI
>>> implementation which uses two SCFG registers MSIIR and
>>> MSIR to support 32 MSI interrupts for each PCIe controller.
>>> The patch is to support it.
>>>
>>> Signed-off-by: Minghuan Lian <Minghuan.Lian@nxp.com>
>>
>> Acked-by: Marc Zyngier <marc.zyngier@arm.com>
>>
>> The DT binding still needs an Ack from the DT maintainers though (cc'd).
> 
> Marc,
> 
> Who will be responsible to pick this driver?  I see you are also one
> of the maintainers for irqchip.  Can you pick up the driver?  The
> binding has already gotten ACKed by the device tree maintainer.

Can you point me to this Ack? I can't see any trace of it in my Inbox.

Thanks,

	M.
-- 
Jazz is not dead. It just smells funny...

Thread

Re: [PATCH 2/2 v5] irqchip/Layerscape: Add SCFG MSI controller support Leo Li <pku.leo@gmail.com> - 2016-04-22 07:40 +0200
  Re: [PATCH 2/2 v5] irqchip/Layerscape: Add SCFG MSI controller  support Marc Zyngier <marc.zyngier@arm.com> - 2016-04-22 09:50 +0200
    RE: [PATCH 2/2 v5] irqchip/Layerscape: Add SCFG MSI controller  support Minghuan Lian <minghuan.lian@nxp.com> - 2016-04-22 10:00 +0200
      Re: [PATCH 2/2 v5] irqchip/Layerscape: Add SCFG MSI controller  support Marc Zyngier <marc.zyngier@arm.com> - 2016-04-22 10:00 +0200

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