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Groups > linux.kernel > #1363545
| From | Maxime Ripard <maxime.ripard@free-electrons.com> |
|---|---|
| Newsgroups | linux.kernel |
| Subject | [PATCH v3 18/19] ARM: sun5i: r8: Add display blocks to the DTSI |
| Date | 2016-03-23 17:50 +0100 |
| Message-ID | <rfU8P-6dp-31@gated-at.bofh.it> (permalink) |
| References | <rfTZ8-69G-21@gated-at.bofh.it> |
| Organization | linux.* mail to news gateway |
The TCON, tv-encoder and display engine backends and frontends are combined
to create our display pipeline.
Add them to the R8 DTSI. It's supposed to be perfectly compatible with the
A10s and A13, but since we haven't tested it on them yet, it's safer to
just enable it on the R8. Eventually, it should be moved to sun5i.dtsi
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
---
arch/arm/boot/dts/sun5i-r8.dtsi | 137 ++++++++++++++++++++++++++++++++++++++++
1 file changed, 137 insertions(+)
diff --git a/arch/arm/boot/dts/sun5i-r8.dtsi b/arch/arm/boot/dts/sun5i-r8.dtsi
index 691d3de75b35..df20b3b3ecfb 100644
--- a/arch/arm/boot/dts/sun5i-r8.dtsi
+++ b/arch/arm/boot/dts/sun5i-r8.dtsi
@@ -57,4 +57,141 @@
status = "disabled";
};
};
+
+ soc@01c00000 {
+ tve0: tv-encoder@01c0a000 {
+ compatible = "allwinner,sun4i-a10-tv-encoder";
+ reg = <0x01c0a000 0x1000>;
+ clocks = <&ahb_gates 34>;
+ resets = <&tcon_ch0_clk 0>;
+ status = "disabled";
+
+ port {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ tve0_in_tcon0: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&tcon0_out_tve0>;
+ };
+ };
+ };
+
+ tcon0: lcd-controller@01c0c000 {
+ compatible = "allwinner,sun5i-a13-tcon";
+ reg = <0x01c0c000 0x1000>;
+ interrupts = <44>;
+ resets = <&tcon_ch0_clk 1>;
+ reset-names = "lcd";
+ clocks = <&ahb_gates 36>,
+ <&tcon_ch0_clk>,
+ <&tcon_ch1_clk>;
+ clock-names = "ahb",
+ "tcon-ch0",
+ "tcon-ch1";
+ clock-output-names = "tcon-pixel-clock";
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ tcon0_in: port@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+
+ tcon0_in_be0: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&be0_out_tcon0>;
+ };
+ };
+
+ tcon0_out: port@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+
+ tcon0_out_tve0: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&tve0_in_tcon0>;
+ };
+ };
+ };
+ };
+
+ fe0: display-frontend@01e00000 {
+ compatible = "allwinner,sun5i-a13-display-frontend";
+ reg = <0x01e00000 0x20000>;
+ interrupts = <47>;
+ clocks = <&ahb_gates 46>, <&de_fe_clk>,
+ <&dram_gates 25>;
+ clock-names = "ahb", "mod",
+ "ram";
+ resets = <&de_fe_clk>;
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ fe0_out: port@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+
+ fe0_out_be0: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&be0_in_fe0>;
+ };
+ };
+ };
+ };
+
+ be0: display-backend@01e60000 {
+ compatible = "allwinner,sun5i-a13-display-backend";
+ reg = <0x01e60000 0x10000>;
+ clocks = <&ahb_gates 44>, <&de_be_clk>,
+ <&dram_gates 26>;
+ clock-names = "ahb", "mod",
+ "ram";
+ resets = <&de_be_clk>;
+ status = "disabled";
+
+ assigned-clocks = <&de_be_clk>;
+ assigned-clock-rates = <300000000>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ be0_in: port@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+
+ be0_in_fe0: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&fe0_out_be0>;
+ };
+ };
+
+ be0_out: port@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+
+ be0_out_tcon0: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&tcon0_in_be0>;
+ };
+ };
+ };
+ };
+ };
+
+ display-engine {
+ compatible = "allwinner,sun5i-a13-display-engine";
+ pipelines = <&be0>;
+ };
};
--
2.7.3
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[PATCH v3 00/19] drm: Add Allwinner A10 display engine support Maxime Ripard <maxime.ripard@free-electrons.com> - 2016-03-23 17:50 +0100
[PATCH v3 16/19] drm: sun4i: tv: Add PAL output standard Maxime Ripard <maxime.ripard@free-electrons.com> - 2016-03-23 17:50 +0100
[PATCH v3 02/19] clk: sunxi: Add display and TCON0 clocks driver Maxime Ripard <maxime.ripard@free-electrons.com> - 2016-03-23 17:50 +0100
[PATCH v3 06/19] ARM: sun5i: dt: Add pll3 and pll7 clocks Maxime Ripard <maxime.ripard@free-electrons.com> - 2016-03-23 17:50 +0100
[PATCH v3 07/19] ARM: sun5i: a13: Add display and TCON clocks Maxime Ripard <maxime.ripard@free-electrons.com> - 2016-03-23 17:50 +0100
[PATCH v3 05/19] dt-bindings: clk: sun5i: add DRAM gates compatible Maxime Ripard <maxime.ripard@free-electrons.com> - 2016-03-23 17:50 +0100
[PATCH v3 15/19] drm: sun4i: Add composite output Maxime Ripard <maxime.ripard@free-electrons.com> - 2016-03-23 17:50 +0100
[PATCH v3 19/19] ARM: sun5i: chip: Enable the TV Encoder Maxime Ripard <maxime.ripard@free-electrons.com> - 2016-03-23 17:50 +0100
[PATCH v3 08/19] ARM: sun5i: Add DRAM gates Maxime Ripard <maxime.ripard@free-electrons.com> - 2016-03-23 17:50 +0100
Re: [linux-sunxi] [PATCH v3 08/19] ARM: sun5i: Add DRAM gates Chen-Yu Tsai <wens@csie.org> - 2016-03-24 05:40 +0100
Re: [linux-sunxi] [PATCH v3 08/19] ARM: sun5i: Add DRAM gates Maxime Ripard <maxime.ripard@free-electrons.com> - 2016-03-29 12:10 +0200
[PATCH v3 18/19] ARM: sun5i: r8: Add display blocks to the DTSI Maxime Ripard <maxime.ripard@free-electrons.com> - 2016-03-23 17:50 +0100
[PATCH v3 10/19] drm: fb: Add seq_file definition Maxime Ripard <maxime.ripard@free-electrons.com> - 2016-03-23 17:50 +0100
[PATCH v3 01/19] clk: composite: Add unregister function Maxime Ripard <maxime.ripard@free-electrons.com> - 2016-03-23 17:50 +0100
[PATCH v3 17/19] drm: sun4i: tv: Add NTSC output standard Maxime Ripard <maxime.ripard@free-electrons.com> - 2016-03-23 17:50 +0100
[PATCH v3 04/19] clk: sunxi: Add TCON channel1 clock Maxime Ripard <maxime.ripard@free-electrons.com> - 2016-03-23 17:50 +0100
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