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Groups > linux.kernel > #1353674
| From | Heiko Stuebner <heiko@sntech.de> |
|---|---|
| Newsgroups | linux.kernel |
| Subject | Re: [RESEND PATCH v2 1/5] clk: rockchip: add more mux parameters for new pll sources |
| Date | 2016-03-09 02:20 +0100 |
| Message-ID | <raAX8-Er-21@gated-at.bofh.it> (permalink) |
| References | <r7Pzj-7L5-5@gated-at.bofh.it> <r7Pzk-7L5-19@gated-at.bofh.it> |
| Organization | linux.* mail to news gateway |
Am Dienstag, 1. März 2016, 18:14:31 schrieb Xing Zheng: > Thers are only two parent PLLs that APLL and GPLL for core on the > previous SoCs (RK3066/RK3188/RK3288/RK3368). Hence, we set fixed > GPLL as alternate parent when core is switching freq. > > Since RK3399 big.LITTLE architecture, we need to select and adapt > more PLLs (ALPLL/ABPLL/DPLL/GPLL) sources. > > Signed-off-by: Xing Zheng <zhengxing@rock-chips.com> note to self: looks good to go
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Re: [RESEND PATCH v2 1/5] clk: rockchip: add more mux parameters for new pll sources Heiko Stuebner <heiko@sntech.de> - 2016-03-09 02:20 +0100
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