Re: PCIe MSI address is not written at pci_enable_msi_range call

From	Marc Zyngier <marc.zyngier@arm.com>
Newsgroups	linux.kernel
Subject	Re: PCIe MSI address is not written at pci_enable_msi_range call
Date	2016-07-13 10:40 +0200
Message-ID	<rUnS2-vb-13@gated-at.bofh.it> (permalink)
References	(2 earlier) <rTFR0-59c-15@gated-at.bofh.it> <rU8gh-6Wm-3@gated-at.bofh.it> <rUlQd-7Gd-3@gated-at.bofh.it> <rUnyG-oj-5@gated-at.bofh.it> <rUnS2-vb-15@gated-at.bofh.it>
Organization	ARM Ltd

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On 13/07/16 09:33, Bharat Kumar Gogada wrote:
>> Subject: Re: PCIe MSI address is not written at pci_enable_msi_range call
>>
>> On 13/07/16 07:22, Bharat Kumar Gogada wrote:
>>>> Subject: Re: PCIe MSI address is not written at pci_enable_msi_range
>>>> call
>>>>
>>>> On 11/07/16 10:33, Bharat Kumar Gogada wrote:
>>>>> Hi Marc,
>>>>>
>>>>> Thanks for the reply.
>>>>>
>>>>> From PCIe Spec:
>>>>> MSI Enable Bit:
>>>>> If 1 and the MSI-X Enable bit in the MSI-X Message Control register
>>>>> (see Section 6.8.2.3) is 0, the function is permitted to use MSI to
>>>>> request service and is prohibited from using its INTx# pin.
>>>>>
>>>>> From Endpoint perspective, MSI Enable = 1 indicates MSI can be used
>>>> which means MSI address and data fields are available/programmed.
>>>>>
>>>>> In our SoC whenever MSI Enable goes from 0 --> 1 the hardware
>>>>> latches
>>>> onto MSI address and MSI data values.
>>>>>
>>>>> With current MSI implementation in kernel, our SoC is latching on to
>>>>> incorrect address and data values, as address/data are updated much
>>>>> later
>>>> than MSI Enable bit.
>>>>
>>>> As a side question, how does setting the affinity work on this
>>>> end-point if this involves changing the address programmed in the MSI
>> registers?
>>>> Do you expect the enabled bit to be toggled to around the write?
>>>>
>>>
>>> Yes,
>>
>> Well, that's pretty annoying, as this will not work either. But maybe your MSI
>> controller has a single doorbell? You haven't mentioned which HW that is...
>>
> The MSI address/data is located in config space, in our SoC for the logic behind PCIe
> to become aware of new address/data  MSI enable transition is used (0 to 1).
> The logic cannot keep polling these registers in configuration space as it would consume power.
> 
> So the logic uses the transition in MSI enable to latch on to address/data.

I understand the "why". I'm just wondering if your SoC needs to have
the MSI address changed when changing the affinity of the MSI? What MSI
controller are you using? Is it in mainline?

Thanks,

	M.
-- 
Jazz is not dead. It just smells funny...

Thread

PCIe MSI address is not written at pci_enable_msi_range call Bharat Kumar Gogada <bharat.kumar.gogada@xilinx.com> - 2016-07-11 04:50 +0200
  Re: PCIe MSI address is not written at pci_enable_msi_range call Marc Zyngier <marc.zyngier@arm.com> - 2016-07-11 10:50 +0200
    RE: PCIe MSI address is not written at pci_enable_msi_range call Bharat Kumar Gogada <bharat.kumar.gogada@xilinx.com> - 2016-07-11 11:40 +0200
      Re: PCIe MSI address is not written at pci_enable_msi_range call Marc Zyngier <marc.zyngier@arm.com> - 2016-07-11 12:30 +0200
        RE: PCIe MSI address is not written at pci_enable_msi_range call Bharat Kumar Gogada <bharat.kumar.gogada@xilinx.com> - 2016-07-11 13:00 +0200
          Re: PCIe MSI address is not written at pci_enable_msi_range call Marc Zyngier <marc.zyngier@arm.com> - 2016-07-11 18:00 +0200
            RE: PCIe MSI address is not written at pci_enable_msi_range call Bharat Kumar Gogada <bharat.kumar.gogada@xilinx.com> - 2016-07-12 11:20 +0200
              Re: PCIe MSI address is not written at pci_enable_msi_range call Marc Zyngier <marc.zyngier@arm.com> - 2016-07-12 16:30 +0200
      Re: PCIe MSI address is not written at pci_enable_msi_range call Marc Zyngier <marc.zyngier@arm.com> - 2016-07-12 18:00 +0200
        RE: PCIe MSI address is not written at pci_enable_msi_range call Bharat Kumar Gogada <bharat.kumar.gogada@xilinx.com> - 2016-07-13 08:30 +0200
          Re: PCIe MSI address is not written at pci_enable_msi_range call Marc Zyngier <marc.zyngier@arm.com> - 2016-07-13 10:20 +0200
            Re: PCIe MSI address is not written at pci_enable_msi_range call Marc Zyngier <marc.zyngier@arm.com> - 2016-07-13 10:40 +0200
              RE: PCIe MSI address is not written at pci_enable_msi_range call Bharat Kumar Gogada <bharat.kumar.gogada@xilinx.com> - 2016-07-13 11:20 +0200
                Re: PCIe MSI address is not written at pci_enable_msi_range call Marc Zyngier <marc.zyngier@arm.com> - 2016-07-13 11:20 +0200
                RE: PCIe MSI address is not written at pci_enable_msi_range call Bharat Kumar Gogada <bharat.kumar.gogada@xilinx.com> - 2016-07-13 11:40 +0200
                Re: PCIe MSI address is not written at pci_enable_msi_range call Marc Zyngier <marc.zyngier@arm.com> - 2016-07-13 11:50 +0200
                RE: PCIe MSI address is not written at pci_enable_msi_range call Bharat Kumar Gogada <bharat.kumar.gogada@xilinx.com> - 2016-07-13 17:40 +0200
                Re: PCIe MSI address is not written at pci_enable_msi_range call Marc Zyngier <marc.zyngier@arm.com> - 2016-07-13 17:50 +0200
            RE: PCIe MSI address is not written at pci_enable_msi_range call Bharat Kumar Gogada <bharat.kumar.gogada@xilinx.com> - 2016-07-13 10:40 +0200
              Re: PCIe MSI address is not written at pci_enable_msi_range call Marc Zyngier <marc.zyngier@arm.com> - 2016-07-20 14:20 +0200

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